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Milan Stanic
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2010 – 2019
- 2018
- [j2]Ivan Ratkovic
, Oscar Palomar
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 639-652 (2018) - 2017
- [b1]Milan Stanic:
Design of energy-efficient vector units for in-order cores. Polytechnic University of Catalonia, Spain, 2017 - [j1]Milan Stanic, Oscar Palomar
An Integrated Vector-Scalar Design on an In-Order ARM Core. ACM Trans. Archit. Code Optim. 14(2): 17:1-17:26 (2017) - 2016
- [c10]Milan Stanic, Oscar Palomar
POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core. PACT 2016: 447-448 - [c9]Milan Stanic, Oscar Palomar
Towards low-power embedded vector processor. Conf. Computing Frontiers 2016: 339-342 - [c8]Ivan Ratkovic, Oscar Palomar
A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques. ISLPED 2016: 362-367 - 2015
- [c7]Ivan Ratkovic, Oscar Palomar
Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors. ISVLSI 2015: 19-26 - [c6]Milovan Duric, Milan Stanic, Ivan Ratkovic, Oscar Palomar
Imposing coarse-grained reconfiguration to general purpose processors. SAMOS 2015: 42-51 - 2014
- [c5]Milan Stanic, Oscar Palomar
VALib and SimpleVector: tools for rapid initial research on vector architectures. Conf. Computing Frontiers 2014: 7:1-7:10 - [c4]Milan Stanic, Oscar Palomar
Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi. HPCS 2014: 47-54 - [c3]Ivan Ratkovic, Oscar Palomar
Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders. ISVLSI 2014: 118-123 - [c2]Milovan Duric, Oscar Palomar
Dynamic-vector execution on a general purpose EDGE chip multiprocessor. ICSAMOS 2014: 18-25 - 2013
- [c1]Ivan Ratkovic, Oscar Palomar
On the selection of adder unit in energy efficient vector processing. ISQED 2013: 143-150
Coauthor Index
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