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Ching-Nen Peng
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2010 – 2019
- 2017
- [j5]Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test 34(3): 50-58 (2017) - [j4]Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers 66(8): 1293-1301 (2017) - 2016
- [j3]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test 33(2): 30-39 (2016) - [j2]Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers 65(3): 770-780 (2016) - [c7]Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC 2016: 58:1-58:6 - 2014
- [j1]Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng:
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. IEEE Des. Test 31(4): 16-26 (2014) - [c6]Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Wafer Level Chip Scale Package copper pillar probing. ITC 2014: 1-6 - [c5]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Redundancy architectures for channel-based 3D DRAM yield improvement. ITC 2014: 1-7 - [c4]Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen:
A novel DFT architecture for 3DIC test, diagnosis and repair. VLSI-DAT 2014: 1-4 - [c3]Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang:
A 4-GHz universal high-frequency on-chip testing platform for IP validation. VTS 2014: 1-6 - 2013
- [c2]Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch. ITC 2013: 1-10 - 2012
- [c1]Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang:
A memory yield improvement scheme combining built-in self-repair and error correction codes. ITC 2012: 1-9
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