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Andreas Tockhorn
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2010 – 2019
- 2013
- [c9]Martin Gag, Tim Wegner, Philipp Gorski, Andreas Tockhorn, Dirk Timmermann:
System level modeling of Networks-on-Chip for power estimation and design space exploration. MBMV 2013: 25-34 - 2012
- [c8]Hagen Sämrow, Claas Cornelius, Philipp Gorski, Andreas Tockhorn, Dirk Timmermann
:
Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown. DDECS 2012: 12-15 - 2011
- [c7]Hagen Sämrow, Claas Cornelius, Philipp Gorski, Jakob Salzmann, Andreas Tockhorn, Dirk Timmermann
Functional enhancements of TMR for power efficient and error resilient ASIC designs. DDECS 2011: 183-188 - 2010
- [c6]Andreas Tockhorn, Claas Cornelius, Hagen Sämrow, Dirk Timmermann
Modeling temperature distribution in Networks-on-Chip using RC-circuits. DDECS 2010: 229-232 - [c5]Tim Wegner, Claas Cornelius, Andreas Tockhorn, Dirk Timmermann:
Monitoring and Control of Temperature in Networks-on-Chip. MEMICS 2010: 124-131
2000 – 2009
- 2009
- [c4]Hagen Sämrow, Claas Cornelius, Frank Sill
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown. SBCCI 2009 - 2008
- [c3]Harald Widiger, Andreas Tockhorn, Dirk Timmermann
On the Impact of Caching for High Performance Packet Classifiers. GLOBECOM 2008: 2314-2318 - 2007
- [c2]Harald Widiger, Andreas Tockhorn, Ralf Salomon, Dirk Timmermann
Accelerating the Evolution of Evolvable Hardware-based Packet Classifiers. WEAH 2007: 27-34 - 2006
- [c1]Ralf Salomon, Harald Widiger, Andreas Tockhorn:
Rapid Evolution of Time-Efficient Packet Classifiers. IEEE Congress on Evolutionary Computation 2006: 2793-2799
Coauthor Index
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