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Chi-Ray Huang
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2020 – today
- 2021
- [j2]Chi-Ray Huang
, Lih-Yih Chiou
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1586-1590 (2021)
2010 – 2019
- 2019
- [c5]Lih-Yih Chiou, Chi-Ray Huang, Chang-Chieh Cheng, Jing-Yu Huang, Wei-Suo Ling:
A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs. VLSI-DAT 2019: 1-4 - 2018
- [j1]Chi-Ray Huang
Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation. IET Circuits Devices Syst. 12(6): 713-719 (2018) - [c4]Chi-Ray Huang, Kuan-Lin Wu, Chung-Han Wu, Lih-Yih Chiou:
Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme. ISCAS 2018: 1-4 - 2014
- [c3]Lih-Yih Chiou, Chi-Ray Huang, Ming-Hung Wu:
A power-efficient pulse-based in-situ timing error predictor for PVT-variation sensitive circuits. ISCAS 2014: 1215-1218 - [c2]Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou:
An ultra-low-power adaptive-body-bias control for subthreshold circuits. VLSI-DAT 2014: 1-4 - 2012
- [c1]Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou:
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion. ISCAS 2012: 2553-2556
Coauthor Index
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