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Peng Cao 0002
Person information
- affiliation: Southeast University, National ASIC System Engineering Research Center, Nanjing, China
Other persons with the same name
- Peng Cao — disambiguation page
- Peng Cao 0001
— Northeastern University, Computer Science and Engineering, Shenyang, China (and 1 more)
- Peng Cao 0003
- Peng Cao 0004 — Peking University, School of Electronics Engineering and Computer Science, Beijing, China
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2020 – today
- 2024
- [j33]Yuqiang Cui
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS. Integr. 94: 102094 (2024) - [c25]Tao Bai
Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning. MLCAD 2024: 27:1-27:7 - 2023
- [j32]Weiwei Shan, Yuqiang Cui, Wentao Dai, Xinning Liu, Jingjing Guo, Peng Cao, Jun Yang:
An efficient path delay variability model for wide-voltage-range digital circuits. Sci. China Inf. Sci. 66(2) (2023) - [j31]Peng Cao
Topology-Aided Multicorner Timing Predictor for Wide Voltage Design. IEEE Des. Test 40(1): 62-69 (2023) - [j30]Shan Shen
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1223-1234 (2023) - [j29]Peng Cao
TF-Predictor: Transformer-Based Prerouting Path Delay Prediction Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2227-2237 (2023) - [j28]Peng Cao
Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1413-1424 (2023) - 2022
- [c24]Tai Yang, Guoqing He, Peng Cao:
Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework. ASP-DAC 2022: 184-189 - [c23]Kai Wang, Peng Cao:
A Graph Neural Network Method for Fast ECO Leakage Power Optimization. ASP-DAC 2022: 196-201 - [i1]Shan Shen, Peng Cao, Ming Ling, Longxing Shi:
A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model. CoRR abs/2202.11941 (2022) - 2021
- [j27]Jingjing Guo
Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 931-944 (2021) - [c22]Hao Yan, Xiao Shi, Chengzhen Xuan, Peng Cao, Longxing Shi:
An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage Range. ASP-DAC 2021: 272-277 - [c21]Peng Cao, Wei Bao, Kai Wang, Tai Yang:
A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy. ASP-DAC 2021: 291-296 - [c20]Haiyang Jiang, Bingqian Xu, Peng Cao, Hao Cai:
Analytical Delay Model in Near-Threshold Domain Considering Transition Time. ICTA 2021: 234-235 - 2020
- [c19]Wei Bao, Peng Cao, Hao Cai, Aiguo Bu:
A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design. ACM Great Lakes Symposium on VLSI 2020: 309-314 - [c18]Jingjing Guo, Peng Cao, Mengxiao Li, Zhiyuan Liu, Jun Yang:
Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j26]Peng Cao
An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation. IEEE Access 7: 171515-171524 (2019) - [c17]Peng Cao, Jiangping Wu, Zhiyuan Liu, Jingjing Guo, Jun Yang, Longxing Shi:
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region. ACM Great Lakes Symposium on VLSI 2019: 323-326 - [c16]Peng Cao, Zhiyuan Liu, Jiangping Wu, Jingjing Guo, Jun Yang, Longxing Shi:
A Statistical Timing Model for Low Voltage Design Considering Process Variation. ICCAD 2019: 1-8 - [c15]Peng Cao, Zhiyuan Liu, Bingqian Xu, Jingjing Guo:
A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time. ICECS 2019: 586-589 - [c14]Peng Cao, Zhiyuan Liu, Jingjing Guo, Haoyu Pang, Jiangping Wu, Jun Yang:
Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region. NEWCAS 2019: 1-4 - 2017
- [j25]Chao Wang, Peng Cao, Bo Liu, Jun Yang:
Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach. IEICE Electron. Express 14(6): 20170090 (2017) - [j24]Chao Wang, Peng Cao, Jun Yang:
Efficient AES cipher on coarse-grained reconfigurable architecture. IEICE Electron. Express 14(11): 20170449 (2017) - [j23]Peng Cao
Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2321-2331 (2017) - 2016
- [j22]Weiwei Shan, Wentao Dai, Youhua Shi
Timing monitoring paths selection for wide voltage IC. IEICE Electron. Express 13(8): 20160095 (2016) - [j21]Jinjiang Yang, Ge Wei, Peng Cao, Jun Yang:
An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers. IEICE Electron. Express 13(11): 20160138 (2016) - 2015
- [j20]Xinning Liu, Yuxiang Niu, Jun Yang, Peng Cao:
A GPS Bit Synchronization Method Based on Frequency Compensation. IEICE Trans. Commun. 98-B(4): 746-753 (2015) - [j19]Chen Yang, Leibo Liu
Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array. J. Circuits Syst. Comput. 24(3): 1550043:1-1550043:21 (2015) - [j18]Leibo Liu
An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. IEEE Trans. Multim. 17(10): 1706-1720 (2015) - [j17]Leibo Liu
Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". IEEE Trans. Multim. 17(12): 2354-2355 (2015) - 2014
- [j16]Leibo Liu
Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor. Sci. China Inf. Sci. 57(8): 1-14 (2014) - [j15]Weiwei Shan, Xiao Zhang, Xingyuan Fu, Peng Cao:
VLSI design of a reconfigurable S-box based on memory sharing method. IEICE Electron. Express 11(1): 20130872 (2014) - [j14]Dong Wang, Peng Cao, Yang Xiao:
A parallel arithmetic array for accelerating compute-intensive applications. IEICE Electron. Express 11(4): 20130981 (2014) - [j13]Dong Wang, Peng Cao, Yang Xiao:
Reduced-error constant correction truncated multiplier. IEICE Electron. Express 11(13): 20140481 (2014) - [j12]Yansheng Wang, Leibo Liu
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 983-994 (2014) - [c13]Bo Liu, Wan-Yu Zhu, Yang Liu, Peng Cao:
A Configuration Compression Approach for Coarse-Grain Reconfigurable Architecture for Radar Signal Processing. CyberC 2014: 448-453 - [c12]Chen Yang, Leibo Liu
Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. FPL 2014: 1-4 - [c11]Chen Mei, Peng Cao, Yang Zhang, Bo Liu, Leibo Liu
Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications. IPDPS Workshops 2014: 281-286 - 2013
- [j11]Yansheng Wang, Leibo Liu
Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. Sci. China Inf. Sci. 56(11): 1-20 (2013) - [j10]Weiwei Shan, Haolin Gu, Bo Li, Xiaoqing Wu, Haikun Jin, Yintao Guo, Peng Cao:
An improved timing monitor for deep dynamic voltage scaling system. IEICE Electron. Express 10(6): 20130089 (2013) - [j9]Hung K. Nguyen, Peng Cao, Xuexiang Wang, Jun Yang, Longxing Shi, Min Zhu, Leibo Liu
Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip. IEICE Trans. Inf. Syst. 96-D(3): 601-615 (2013) - [j8]Gugang Gao, Peng Cao, Jun Yang, Longxing Shi:
Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC. IEICE Trans. Inf. Syst. 96-D(8): 1654-1666 (2013) - [j7]Yansheng Wang, Leibo Liu
The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(11): 2218-2229 (2013) - [j6]Weiwei Shan, Xin Chen
Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware. IEEE Trans. Instrum. Meas. 62(10): 2716-2724 (2013) - [j5]Chen Mei, Min Li, Peng Cao, Amir Amin, Chunshu Li, Jun Yang, Antoine Dejonghe, Liesbet Van der Perre
Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor. IEEE Trans. Signal Process. 61(18): 4438-4449 (2013) - [c10]Wen Wen
A Robust and Efficient Minutia-Based Fingerprint Matching Algorithm. ACPR 2013: 201-205 - [c9]Leibo Liu
An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. CICC 2013: 1-4 - [c8]Leibo Liu
Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor. ISCAS 2013: 897-900 - 2012
- [j4]Xinning Liu, Chen Mei, Peng Cao, Min Zhu, Longxing Shi:
Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. IEICE Trans. Inf. Syst. 95-D(2): 374-382 (2012) - [j3]Bo Liu, Peng Cao, Min Zhu, Jun Yang, Leibo Liu
Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. IEICE Trans. Inf. Syst. 95-D(7): 1858-1871 (2012) - [c7]Peng Cao, Huiyan Jiang, Bo Liu, Weiwei Shan:
Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture. CyberC 2012: 228-231 - [c6]Peng Cao, Yong Cai, Bo Liu, Weiwei Shan:
Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array. CyberC 2012: 286-291 - [c5]Jie Li, Xinxiang Ke, Peng Cao, Weiwei Shan:
A New Approach to Implement Discrete Wavelet Transform on Coarse-Grained Reconfigurable Architecture. CyberC 2012: 292-297 - [c4]Bo Liu, Peng Cao, Jinjiang Yang:
Hybrid-Priority Configuration Cache Supervision Method for Coarse Grained Reconfigurable Architecture. CyberC 2012: 408-414 - [c3]Chen Mei, Min Li, Peng Cao, Amir Amin, Chunshu Li, Sofie Pollin
Exploration of Full HD Media Decoding on SDR Baseband Processor. SiPS 2012: 185-190 - 2010
- [j2]Peng Cao, Chao Wang, Longxing Shi:
Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme. J. Signal Process. Syst. 61(2): 219-230 (2010)
2000 – 2009
- 2009
- [j1]Peng Cao, Chao Wang, Longxing Shi:
Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(8): 2000-2008 (2009) - [c2]Peng Cao, Chao Wang, Jun Yang, Longxing Shi:
Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer. ICME 2009: 1094-1097 - 2007
- [c1]Chao Wang, Wu Zhilin, Peng Cao, Li Jie:
An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform. ICME 2007: 1575-1578
Coauthor Index
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last updated on 2024-11-15 19:34 CET by the dblp team
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