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John A. Nestor
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2020 – today
- 2021
- [c19]John A. Nestor:
Experiences with Remote Teaching an Embedded Systems Course. ACM Great Lakes Symposium on VLSI 2021: 437-442
2010 – 2019
- 2017
- [c18]John A. Nestor:
From microelectronics to making: Incorporating microelectronics in a first-year engineering course. MSE 2017: 27-30 - 2011
- [c17]John F. Greco, John A. Nestor:
An undergraduate embedded systems project. MSE 2011: 43-46 - [c16]John A. Nestor:
HDL coding guidelines for student projects. MSE 2011: 86-89 - 2010
- [c15]Berkin Ilbeyi, John A. Nestor:
VCache: visualization applet for processor caches. ITiCSE 2010: 304
2000 – 2009
- 2009
- [c14]John A. Nestor, Chris Nadovich:
An FPGA-based wireless network capstone project. MSE 2009: 53-56 - 2008
- [j6]John A. Nestor:
Experience With the CADAPPLETS Project. IEEE Trans. Educ. 51(3): 342-348 (2008) - 2007
- [c13]John A. Nestor, Jeremy Lavine:
L4: An FPGA-Based Accelerator for Detailed Maze Routing. FPL 2007: 357-362 - [c12]John A. Nestor:
Experience with the CADAPPLETS Project. MSE 2007: 169-170 - 2005
- [j5]John A. Nestor:
L3: An FPGA-based multilayer maze routing accelerator. Microprocess. Microsystems 29(2-3): 87-97 (2005) - [c11]John A. Nestor:
Teaching Computer Organization with HDLs: An Incremental Approach. MSE 2005: 77-78 - 2003
- [c10]John A. Nestor:
FPGA Implementation of a Maze Routing Accelerator. FPL 2003: 992-995 - [c9]John A. Nestor, David A. Rich:
Integrating Digital, Analog, and Mixed-Signal Design in an Undergraduate ECE Curriculum. MSE 2003: 89-90 - 2002
- [c8]John A. Nestor:
A new look at hardware maze routing. ACM Great Lakes Symposium on VLSI 2002: 142-147 - 2001
- [c7]John A. Nestor:
Web-Based Visualization Tools for Teaching VLSI CAD Algorithms. MSE 2001: 100-101
1990 – 1999
- 1993
- [j4]John A. Nestor, Ganesh Krishnamoorthy:
SALSA: a new approach to scheduling with timing constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1107-1122 (1993) - [j3]John A. Nestor:
Visual register-transfer description of VLSI microarchitectures. IEEE Trans. Very Large Scale Integr. Syst. 1(1): 72-76 (1993) - [c6]Michael R. Rhinehart, John A. Nestor:
SALSE II: A Fast Transformational Scheduler for High-level Synthesis. ISCAS 1993: 1678-1681 - 1992
- [c5]Ganesh Krishnamoorthy, John A. Nestor:
Data Path Allocation using an Extended Binding Model. DAC 1992: 279-284 - 1990
- [c4]John A. Nestor, Ganesh Krishnamoorthy:
SALSA: A New Approach to Scheduling with Timing Constraints. ICCAD 1990: 262-265
1980 – 1989
- 1989
- [c3]John A. Nestor, Bassel Soudan
, Zubair Mayet:
MIES: a microarchitecture design tool. MICRO 1989: 217-222 - 1988
- [c2]Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn:
The System Architect's Workbench. DAC 1988: 337-343 - 1984
- [j2]David P. LaPotin, Sani R. Nassif, Jayanth V. Rajan, Michael L. Bushnell, John A. Nestor:
DIF: A framework for VLSI multi-level representation. Integr. 2(3): 227-241 (1984) - 1983
- [j1]Donald E. Thomas, John A. Nestor:
Defining and Implementing a Multilevel Design Representation with Simulation Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(3): 135-145 (1983) - 1982
- [c1]John A. Nestor, Donald E. Thomas:
Defining and implementing a multilevel design representation with simulation applications. DAC 1982: 740-746
Coauthor Index
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