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Radu Teodorescu
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2020 – today
- 2024
- [c39]Saikat Majumdar, Radu Teodorescu:
Voltage Noise-Based Adversarial Attacks on Machine Learning Inference in Multi-Tenant FPGA Accelerators. HOST 2024: 80-85 - 2023
- [c38]Moein Ghaniyoun
, Kristin Barber
TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments. ISCA 2023: 35:1-35:15 - 2022
- [j9]Kristin Barber
A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications. IEEE Comput. Archit. Lett. 21(1): 9-12 (2022) - [j8]Sudhanva Gurumurthi
Special Issue on Top Picks From the 2021 Computer Architecture Conferences. IEEE Micro 42(4): 6-9 (2022) - [c37]Saikat Majumdar, Mohammad Hossein Samavatian, Radu Teodorescu:
Characterizing Side-Channel Leakage of DNN Classifiers though Performance Counters. HOST 2022: 45-48 - [c36]Jiuqin Zhou, Yuan Xiao, Radu Teodorescu, Yinqian Zhang:
ENCLYZER: Automated Analysis of Transient Data Leaks on Intel SGX. SEED 2022: 145-156 - [c35]Mengyuan Li, Luca Wilke
A Systematic Look at Ciphertext Side Channels on AMD SEV-SNP. SP 2022: 337-351 - [i6]Mohammad Hossein Samavatian, Saikat Majumdar, Kristin Barber, Radu Teodorescu:
DNNShield: Dynamic Randomized Model Sparsification, A Defense Against Adversarial Machine Learning. CoRR abs/2208.00498 (2022) - 2021
- [c34]Jia Guo, Radu Teodorescu, Gagan Agrawal:
Fused DSConv: Optimizing Sparse CNN Inference for Execution on Edge Devices. CCGRID 2021: 545-554 - [c33]Jia Guo, Radu Teodorescu, Gagan Agrawal:
A Fused Inference Design for Pattern-Based Sparse CNN on Edge Devices. HiPC 2021: 424-429 - [c32]Saikat Majumdar, Mohammad Hossein Samavatian, Kristin Barber, Radu Teodorescu:
Using Undervolting as an on-Device Defense Against Adversarial Machine Learning Attacks. HOST 2021: 158-169 - [c31]Moein Ghaniyoun, Kristin Barber, Yinqian Zhang, Radu Teodorescu:
INTROSPECTRE: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities. ISCA 2021: 874-887 - [i5]Mohammad Hossein Samavatian, Saikat Majumdar, Kristin Barber, Radu Teodorescu:
HASI: Hardware-Accelerated Stochastic Inference, A Defense Against Adversarial Machine Learning Attacks. CoRR abs/2106.05825 (2021) - [i4]Saikat Majumdar, Mohammad Hossein Samavatian, Kristin Barber, Radu Teodorescu:
Using Undervolting as an On-Device Defense Against Adversarial Machine Learning Attacks. CoRR abs/2107.09804 (2021) - 2020
- [j7]Mohammad Hossein Samavatian, Anys Bacha, Li Zhou, Radu Teodorescu
RNNFast: An Accelerator for Recurrent Neural Networks Using Domain-Wall Memory. ACM J. Emerg. Technol. Comput. Syst. 16(4): 38:1-38:27 (2020) - [c30]Jia Guo, Radu Teodorescu, Gagan Agrawal:
A Pattern-Based API for Mapping Applications to a Hierarchy of Multi-Core Devices. CCGRID 2020: 11-20 - [c29]Yuan Xiao, Yinqian Zhang, Radu Teodorescu:
SPEECHMINER: A Framework for Investigating and Measuring Speculative Execution Vulnerabilities. NDSS 2020
2010 – 2019
- 2019
- [j6]Kristin Barber, Anys Bacha
Isolating Speculative Data to Prevent Transient Execution Attacks. IEEE Comput. Archit. Lett. 18(2): 178-181 (2019) - [c28]Kristin Barber, Anys Bacha, Li Zhou, Yinqian Zhang, Radu Teodorescu:
SpecShield: Shielding Speculative Data from Microarchitectural Covert Channels. PACT 2019: 151-164 - [c27]Li Zhou, Mohammad Hossein Samavatian, Anys Bacha, Saikat Majumdar, Radu Teodorescu:
Adaptive parallel execution of deep neural networks on heterogeneous edge devices. SEC 2019: 195-208 - [c26]Sobhan Moosavi, Mohammad Hossein Samavatian, Srinivasan Parthasarathy
Accident Risk Prediction based on Heterogeneous Sparse Data: New Dataset and Insights. SIGSPATIAL/GIS 2019: 33-42 - [c25]Li Zhou, Hao Wen, Radu Teodorescu, David H. C. Du:
Distributing Deep Neural Networks with Containerized Partitions at the Edge. HotEdge 2019 - [i3]Sobhan Moosavi, Mohammad Hossein Samavatian, Srinivasan Parthasarathy, Radu Teodorescu, Rajiv Ramnath:
Accident Risk Prediction based on Heterogeneous Sparse Data: New Dataset and Insights. CoRR abs/1909.09638 (2019) - [i2]Yuan Xiao, Yinqian Zhang, Radu Teodorescu:
SPEECHMINER: A Framework for Investigating and Measuring Speculative Execution Vulnerabilities. CoRR abs/1912.00329 (2019) - 2018
- [c24]Xiang Pan, Anys Bacha, Spencer Rudolph, Li Zhou, Yinqian Zhang, Radu Teodorescu:
NVCool: When Non-Volatile Caches Meet Cold Boot Attacks. ICCD 2018: 439-448 - [c23]Li Zhou, Ren Chen, Yinglong Xia, Radu Teodorescu:
C-Graph: A Highly Efficient Concurrent Graph Reachability Query Framework. ICPP 2018: 79:1-79:10 - [i1]Mohammad Hossein Samavatian, Anys Bacha, Li Zhou, Radu Teodorescu:
RNNFast: An Accelerator for Recurrent Neural Networks Using Domain Wall Memory. CoRR abs/1812.07609 (2018) - 2017
- [c22]Xiang Pan, Anys Bacha, Radu Teodorescu:
Respin: Rethinking Near-Threshold Multiprocessor Design with Non-volatile Memory. IPDPS 2017: 265-275 - 2016
- [c21]Renji Thomas, Kristin Barber, Naser Sedaghati, Li Zhou, Radu Teodorescu:
Core tunneling: Variation-aware voltage noise mitigation in GPUs. HPCA 2016: 151-162 - [c20]Renji Thomas, Naser Sedaghati, Radu Teodorescu:
EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures. ISPASS 2016: 79-89 - [c19]Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. MICRO 2016: 54:1-54:12 - [c18]Yuan Xiao, Xiaokuan Zhang, Yinqian Zhang, Radu Teodorescu:
One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation. USENIX Security Symposium 2016: 19-35 - 2015
- [j5]Vadim Axelrod, Radu Teodorescu:
Commentary: When the brain takes a break: a model-based analysis of mind wandering. Frontiers Comput. Neurosci. 9: 83 (2015) - [c17]Anys Bacha, Radu Teodorescu:
Authenticache: harnessing cache ECC for system authentication. MICRO 2015: 128-140 - 2014
- [j4]Venmugil Elango, Naser Sedaghati, Fabrice Rastello, Louis-Noël Pouchet, J. Ramanujam
On Using the Roofline Model with Lower Bounds on Data Movement. ACM Trans. Archit. Code Optim. 11(4): 67:1-67:23 (2014) - [c16]Xiang Pan, Radu Teodorescu:
Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors. PACT 2014: 485-486 - [c15]Xiang Pan, Radu Teodorescu:
NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores. ICCD 2014: 400-407 - [c14]Anys Bacha, Radu Teodorescu:
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors. MICRO 2014: 306-318 - 2013
- [j3]Timothy N. Miller, Nagarjuna Surapaneni, Radu Teodorescu:
Runtime failure rate targeting for energy-efficient reliability in chip microprocessors. Concurr. Comput. Pract. Exp. 25(6): 790-807 (2013) - [c13]Anys Bacha, Radu Teodorescu:
Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors. ISCA 2013: 297-307 - 2012
- [j2]Timothy N. Miller, Renji Thomas, Radu Teodorescu:
Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units. IEEE Comput. Archit. Lett. 11(2): 45-48 (2012) - [c12]Timothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu:
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips. HPCA 2012: 27-38 - [c11]Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu:
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors. ISCA 2012: 249-260 - 2011
- [c10]Naser Sedaghati, Renji Thomas, Louis-Noël Pouchet, Radu Teodorescu, P. Sadayappan:
StVEC: A Vector Instruction Extension for High Performance Stencil Computation. PACT 2011: 276-287 - 2010
- [c9]Timothy N. Miller, Renji Thomas, James Dinan, Bruce M. Adcock, Radu Teodorescu:
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches. MICRO 2010: 351-362 - [c8]Timothy N. Miller, Nagarjuna Surapaneni, Radu Teodorescu:
Flexible Error Protection for Energy Efficient Reliable Architectures. SBAC-PAD 2010: 1-8
2000 – 2009
- 2008
- [c7]Radu Teodorescu, Josep Torrellas:
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. ISCA 2008: 363-374 - 2007
- [c6]Pin Zhou, Radu Teodorescu, Yuanyuan Zhou:
HARD: Hardware-Assisted Lockset-based Race Detection. HPCA 2007: 121-132 - [c5]Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas:
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. MICRO 2007: 27-42 - 2006
- [j1]Radu Teodorescu, Jun Nakano, Josep Torrellas:
SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback. IEEE Micro 26(5): 28-40 (2006) - [c4]Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Michael Kozuch, Todd C. Mowry, Radu Teodorescu, Anastassia Ailamaki, Limor Fix, Gregory R. Ganger, Bin Lin, Steven W. Schlosser:
Log-based architectures for general-purpose monitoring of deployed code. ASID 2006: 63-65 - 2005
- [c3]Radu Teodorescu, Josep Torrellas:
Prototyping Architectural Support for Program Rollback Using FPGAs. FCCM 2005: 23-32 - 2004
- [c2]Lucian Popa, Irina Athanasiu, Costin Raiciu, Raju Pandey, Radu Teodorescu:
Using code collection to support large applications on mobile devices. MobiCom 2004: 16-29 - 2001
- [c1]Radu Teodorescu, Raju Pandey:
Using JIT Compilation and Configurable Runtime Systems for Efficient Deployment of Java Programs on Ubiquitous Devices. UbiComp 2001: 76-95
Coauthor Index
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last updated on 2024-10-07 21:22 CEST by the dblp team
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