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Jin Liu 0004
Person information
- affiliation: University of Texas at Dallas, Department of Electrical Engineering, USA
- affiliation (PhD 1999): Georgia Institute of Technology, Atlanta, GA, USA
Other persons with the same name
- Jin Liu — disambiguation page
- Jin Liu 0001 — Heinrich-Hertz-Institut für Nachrichtentechnik GmbH, Berlin, Germany (and 1 more)
- Jin Liu 0002 — Washington State University, School of Mechanical and Materials Engineering, Pullman, WA, USA
- Jin Liu 0003 — The University of Electro-Communications, Department of Communication Engineering, Tokyo, Japan
- Jin Liu 0005
— University of North Texas Health Science Center, Department of Pharmaceutical Sciences, Fort Worth, TX, USA (and 2 more)
- Jin Liu 0006
- Jin Liu 0007
- Jin Liu 0008
- Jin Liu 0009
- Jin Liu 0010
- Jin Liu 0011
- Jin Liu 0012
- Jin Liu 0013
- Jin Liu 0014
- Jin Liu 0015
- Jin Liu 0016
- Jin Liu 0017 — National Huaqiao University, College of Computer Science and Technology, Xiamen, China (and 1 more)
- Jin Liu 0018
- Jin Liu 0019
- Jin Liu 0020
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2020 – today
- 2024
- [j23]Ziyang Luo
A High-Efficiency 40.68-MHz Single-Stage Dual-Output Regulating Rectifier With ZVS and Synchronous PFM Control for Wireless Powering. IEEE J. Solid State Circuits 59(8): 2418-2429 (2024) - 2023
- [j22]Ziyang Luo
A 40.68-MHz Active Rectifier With Cycle-Based On-/Off-Delay Compensation for High-Current Biomedical Implants. IEEE J. Solid State Circuits 58(2): 345-356 (2023) - 2022
- [j21]Qi Cheng
A Wide-Input-Range Low-Profile Adaptive Delay Compensated Hysteretic LED Driver With Enhanced Current Accuracy. IEEE J. Solid State Circuits 57(8): 2474-2485 (2022) - [j20]Jiu Xiong
A Continuous-Time Sigma-Delta Modulator With Continuous-Time Delay-Based Integrator. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 914-918 (2022) - [c31]Jiu Xiong, Jeniffer Zhao, Jin Liu, Hoi Lee:
A 3rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators. ISCAS 2022: 1230-1233 - [c30]Jesse Coulon, Jin Liu:
A Diode-Based D-2D DAC Architecture with Leakage Current Compensation for Ultra-low Power Application. ISCAS 2022: 1445-1448 - [c29]Weijie Han, Ziyang Luo, Chen Chen, Jin Liu, Hoi Lee:
A 200mA-Load 0.62fs-FOM Active-Capacitor-Assisted Dual-loop Output Capacitorless Low-Dropout Regulator in Standard 65nm CMOS. ISCAS 2022: 1906-1909 - [c28]Chen Chen, Jin Liu, Hoi Lee:
A 2-5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR Boosting Scheme Achievi 1 ng 91% Efficie 1 ncy at a Conversion Ratio of 12. ISSCC 2022: 1-3 - [c27]Chen Chen, Jin Liu, Hoi Lee:
A 2.5-5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network with Capacitor-Assisted Dual-Inductor Filtering. ISSCC 2022: 234-236 - 2021
- [j19]Chen Chen
A 2-MHz 9-45-V Input High-Efficiency Three-Switch ZVS Step-Up/-Down Hybrid Converter. IEEE J. Solid State Circuits 56(3): 855-865 (2021) - [j18]Zhe Hua
A 1.2-A Dual-Output SC DC-DC Regulator With Continuous Gate-Drive Modulation Achieving ≤0.01-mV/mA Cross Regulation. IEEE J. Solid State Circuits 56(5): 1576-1587 (2021) - [c26]Qi Cheng
A 5-100V Input Low-Profile Adaptive Delay Compensated Hysteretic LED Driver with Enhanced Current Accuracy. CICC 2021: 1-2 - [c25]Chang han Rho, Jin-Ku Kang, Jin Liu:
Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit. ISOCC 2021: 333-334 - 2020
- [c24]Chen Chen, Jin Liu, Hoi Lee:
A 9 - 45V Input 2MHz 3-Switch ZVS Step-up / -down Hybrid Converter with 5x Volume Reduction. CICC 2020: 1-4
2010 – 2019
- 2019
- [j17]Lin Cong
A High-Efficiency Low-Profile Zero-Voltage Transition Synchronous Non-Inverting Buck-Boost Converter With Auxiliary-Component Sharing. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 438-449 (2019) - [c23]Jiu Xiong, Jiajun Ren, Jin Liu:
An 8-b 2b/cycle Asynchronous SAR ADC with Capacitive Divider Based RC-DAC. MWSCAS 2019: 762-765 - [c22]Jiajun Ren, Jiu Xiong, Jin Liu:
ADC Quantization with Overlapping Metastability Zones and Dual Reference Calibration. MWSCAS 2019: 896-899 - 2018
- [c21]Jiajun Ren, Jiu Xiong, Jin Liu:
High-Speed ADC Quantization with Overlapping Metastability Zones. MWSCAS 2018: 234-237 - 2017
- [j16]Guanming Huang, Donesh Gillin, Dian Zhou, Jin Liu, Xuan Zeng, Po-Yu Kuo:
An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer. Sci. China Inf. Sci. 60(2): 22401 (2017) - [c20]Yucheng Dai, Yahia R. Ramadan, Hlaing Minn, Jiu Xiong, Jin Liu, Alan Gatherer:
A New Receiver Architecture for MIMO Beam-Forming Applications. GLOBECOM 2017: 1-6 - [c19]Jiu Xiong, Jin Liu, Yucheng Dai, Hlaing Minn:
An open-loop 28GHz 16-phase clock generator in 28nm CMOS. MWSCAS 2017: 305-308 - 2016
- [j15]Xiaochen Yang, Guoping Cui, Yang Zhang, Jiajun Ren, Jin Liu:
A Metastability Error Detection and Reduction Technique for Partially Active Flash ADCs. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 331-335 (2016) - 2014
- [j14]Xiaochen Yang, Jin Liu:
A 10 GS/s 6 b Time-Interleaved Partially Active Flash ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2272-2280 (2014) - 2013
- [j13]Yuxiang Zheng, Jin Liu, Robert Payne, Mark Morgan, Hoi Lee:
A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2274-2285 (2013) - [c18]Xiaochen Yang, Robert Payne, Jin Liu:
A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs. CICC 2013: 1-4 - [c17]Jin Liu, Vinod Mukundagiri:
Study of ADC resolution and bandwidth requirement tradeoffs for high-speed data communications. MWSCAS 2013: 864-867 - 2012
- [j12]Yunlei Li, Jin Liu, Hoi Lee:
Ground Switching Load Modulation With Ground Isolation for Passive HF RFID Transponders. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1443-1452 (2012) - 2011
- [j11]Mengmeng Du, Hoi Lee, Jin Liu:
A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control. IEEE J. Solid State Circuits 46(8): 1928-1939 (2011) - [c16]Xiaochen Yang, Jin Liu:
An open-loop 10GHz 8-phase clock generator in 65nm CMOS. CICC 2011: 1-4 - 2010
- [j10]Junjie Yao, Jin Liu, Hoi Lee:
Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs. IEEE Trans. Circuits Syst. II Express Briefs 57-II(2): 110-114 (2010)
2000 – 2009
- 2009
- [j9]Raymond E. Barnett, Jin Liu, Steve Lazar:
A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders. IEEE J. Solid State Circuits 44(2): 354-370 (2009) - [c15]Jin Liu, Jim Buckwalter:
Gigabit transceivers and building blocks. CICC 2009 - [c14]Hao Liu, Jin Liu, Robert Payne, Cy Cantrell, Mark Morgan:
A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS. CICC 2009: 113-116 - 2008
- [j8]Raymond E. Barnett, Jin Liu:
An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control. IEEE J. Solid State Circuits 43(8): 1808-1815 (2008) - 2007
- [c13]Raymond E. Barnett, Jin Liu:
An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control. CICC 2007: 393-396 - 2006
- [j7]Xiaofeng Lin, Jin Liu, Hoi Lee, Hao Liu:
A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-$muhbox m$CMOS. IEEE J. Solid State Circuits 41(8): 1908-1918 (2006) - [j6]Guangbin Zhang, Sooping Saw, Jin Liu, Scott Sterrantino, David K. Johnson, Sungyong Jung:
An accurate current source with on-chip self-calibration circuits for low-voltage current-mode differential drivers. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(1): 40-47 (2006) - [c12]Raymond E. Barnett, Jin Liu:
A 0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFID. CICC 2006: 769-772 - 2005
- [j5]Xiaofeng Lin, Sooping Saw, Jin Liu:
A CMOS 0.25-μm continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission. IEEE J. Solid State Circuits 40(3): 593-602 (2005) - [j4]Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1915-1924 (2005) - [c11]Xiaofeng Lin, Hoi Lee, Jin Liu:
A continuous-time adaptive FIR equalizer with LNV-AIL delay line for 2.5Gb/s data communication. CICC 2005: 413-416 - [c10]Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. ISCAS (1) 2005: 113-116 - 2004
- [j3]Sungyong Jung, Martin A. Brooke
Parasitic modeling and analysis for a 1-Gb/s CMOS laser driver. IEEE Trans. Circuits Syst. II Express Briefs 51-II(10): 517-522 (2004) - [j2]Xiaofeng Lin, Jin Liu:
A digital power spectrum estimation method for the adaptation of high-speed equalizers. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(12): 2436-2443 (2004) - [c9]Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles C. Chiang:
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. DATE 2004: 1322-1326 - [c8]Youngkyun Jeong, Sungyong Jung, Jin Liu:
A CMOS impulse generator for UWB wireless communication systems. ISCAS (4) 2004: 129-132 - [c7]Stefano Gregori, Yunlei Li, Huijuan Li, Jin Liu, Franco Maloberti:
2.45 GHz power and data transmission for a low-power autonomous sensors platform. ISLPED 2004: 269-273 - 2003
- [c6]Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng:
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. ICCAD 2003: 581-587 - [c5]Guangbin Zhang, Jin Liu, Sungyong Jung:
An accurate current source with on-chip self-calibration circuits for low-voltage differential transmitter drivers. ISCAS (2) 2003: 192-195 - [c4]Xiaofeng Lin, Jin Liu:
A CMOS analog continuous-time FIR filter for 1Gbps cable equalizer. ISCAS (2) 2003: 296-299 - [c3]Xiaofeng Lin, Guangbin Zhang, Jin Liu:
Pulse extraction: a digital power spectrum estimation method for adaptation of Gbps equalizers. ISCAS (1) 2003: 749-752 - 2002
- [j1]Jin Liu, Martin A. Brooke
A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation. IEEE Trans. Neural Networks 13(5): 1178-1186 (2002) - [c2]Guangbin Zhang, Jin Liu:
A robust edge detector for motion detection. ISCAS (4) 2002: 45-48
1990 – 1999
- 1999
- [c1]Jin Liu, Martin A. Brooke:
A fully parallel learning neural network chip for real-time control. IJCNN 1999: 2323-2328
Coauthor Index
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