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Carl Edward Gray
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2020 – today
- 2023
- [c10]Naseem Ahmadpour
, Lian Loke
Understanding how technology can support social-emotional learning of children: a dyadic trauma-informed participatory design with proxies. CHI 2023: 299:1-299:17 - 2021
- [c9]Lian Loke, Aaron Blishen, Carl Gray, Naseem Ahmadpour:
Safety, Connection and Reflection: Designing with Therapists for Children with Serious Emotional Behaviour Issues. CHI 2021: 162:1-162:17
2010 – 2019
- 2013
- [c8]David C. Keezer
Practical methods for extending ATE to 40 and 50Gbps. ITC 2013: 1-10 - 2012
- [b1]Carl Edward Gray:
An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices. Georgia Institute of Technology, Atlanta, GA, USA, 2012 - [c7]David C. Keezer
Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter. ITC 2012: 1-11 - 2011
- [j2]Carl Edward Gray, David C. Keezer
Extending a DWDM Optical Network Test System to 12 Gbps x4 Channels. J. Electron. Test. 27(3): 351-361 (2011) - [c6]Carl Gray, David C. Keezer
Burst-Mode Transmission and Data Recovery for Multi-GHz Optical Packet Switching Network Testing. Asian Test Symposium 2011: 545-551 - [c5]David C. Keezer
Two methods for 24 Gbps test signal synthesis. DATE 2011: 579-582 - 2010
- [j1]David C. Keezer
Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic. J. Electron. Test. 26(1): 87-96 (2010)
2000 – 2009
- 2009
- [c4]David C. Keezer
A development platform and electronic modules for automated test up to 20 Gbps. ITC 2009: 1-11 - 2007
- [c3]Carl Edward Gray, Odile Liboiron-Ladouceur
Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching network. ITC 2007: 1-9 - [i1]David C. Keezer, Carl Gray, Ashraf M. Majid, Nafeez Taher:
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. CoRR abs/0710.4761 (2007) - 2005
- [c2]David C. Keezer
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. DATE 2005: 152-157 - [c1]David C. Keezer
Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components. ESSCIRC 2005: 291-294
Coauthor Index
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