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Weifeng He
Wei-Feng He
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2020 – today
- 2024
- [j37]Rui Qin, Zhifen Zhang
, Jing Huang, Zhengyao Du, Xianwen Xiang
A novel physically interpretable end-to-end network for stress monitoring in laser shock peening. Comput. Ind. 155: 104060 (2024) - [j36]Qichun Hu
Point cloud enhancement optimization and high-fidelity texture reconstruction methods for air material via fusion of 3D scanning and neural rendering. Expert Syst. Appl. 242: 122736 (2024) - [j35]Jieyu Li
TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core. IEEE J. Solid State Circuits 59(2): 605-615 (2024) - [j34]Chuxiong Lin
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip. IEEE J. Solid State Circuits 59(2): 616-625 (2024) - [j33]Xin Wu
Aeroengine Blades Damage Detection and Measurement Based on Multimodality Fusion Learning. IEEE Trans. Instrum. Meas. 73: 1-15 (2024) - [j32]Xin Wu
Research on the Performance State Assessment of Aero-Engine Compressor Driven by Realistic Digital Aero-Engine Structure Model. IEEE Trans. Instrum. Meas. 73: 1-13 (2024) - [c60]Yuxuan Qin, Chuxiong Lin, Mingche Lai, Zhang Luo, Shi Xu, Weifeng He:
Reducing DRAM Latency via In-situ Temperature- and Process-Variation-Aware Timing Detection and Adaption. DAC 2024: 67:1-67:6 - 2023
- [j31]Rui Qin
Surface stress monitoring of laser shock peening using AE time-scale texture image and multi-scale blueprint separable convolutional networks with attention mechanism. Expert Syst. Appl. 224: 120018 (2023) - [j30]Xin Wu, Xiaolong Wei
PointCNT: A One-Stage Point Cloud Registration Approach Based on Complex Network Theory. Remote. Sens. 15(14): 3545 (2023) - [j29]Hao Zhang
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 1015-1028 (2023) - [j28]Yuxuan Qin
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3078-3091 (2023) - [j27]Yanan Sun
BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2048-2061 (2023) - [j26]Yanan Sun
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3198-3211 (2023) - [j25]Bingxi Pei
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3787-3791 (2023) - [j24]Zhifen Zhang
A Novel Approach for Surface Integrity Monitoring in High-Energy Nanosecond-Pulse Laser Shock Peening: Acoustic Emission and Hybrid-Attention CNN. IEEE Trans. Ind. Informatics 19(3): 2802-2813 (2023) - [c59]Dengfeng Wang, Liukai Xu, Songyuan Liu, Zhi Li, Yiming Chen, Weifeng He, Xueqing Li, Yanan Sun:
TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations. ICCAD 2023: 1-9 - [c58]Lin Shao, Mingche Lai, Shi Xu, Chuxiong Lin, Weifeng He:
A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip. ISCAS 2023: 1-5 - [c57]Xue Yuan, Kun Su, Jingyi He, Shi Xu, Jieyu Li
An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations. ISCAS 2023: 1-5 - [c56]Jieyu Li
CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition. ISSCC 2023: 430-431 - [i1]Dengfeng Wang, Liukai Xu, Songyuan Liu, Zhi Li, Yiming Chen, Weifeng He, Xueqing Li, Yanan Sun:
TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations. CoRR abs/2307.02717 (2023) - 2022
- [j23]Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Wei-Feng He:
Hierarchical photoelectric hybrid packet switching network for high-performance computing. JOCN 14(8): 680-690 (2022) - [j22]Shuai Yuan
MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification. IEEE Trans. Geosci. Remote. Sens. 60: 1-17 (2022) - [j21]Zhifen Zhang
Online Evaluation of Surface Hardness for Aluminum Alloy in LSP Using Modal Acoustic Emission. IEEE Trans. Instrum. Meas. 71: 1-10 (2022) - [c55]Jieyu Li
TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption. CICC 2022: 1-2 - [c54]Chuxiong Lin, Weifeng He, Yannan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok:
MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation. CICC 2022: 1-2 - [c53]Liukai Xu, Songyuan Liu, Zhi Li, Dengfeng Wang, Yiming Chen, Yanan Sun, Xueqing Li, Weifeng He, Shi Xu:
CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration. DAC 2022: 115-120 - [c52]Dengfeng Wanq, Zhi Li, Chengjun Chang, Weifeng He, Yanan Sun:
All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations. ICTA 2022: 150-151 - 2021
- [j20]Chuxiong Lin
MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip. IEEE J. Solid State Circuits 56(7): 2270-2280 (2021) - [j19]Zhuojun Liang, Dongxu Lv
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 307-320 (2021) - [c51]Yongjie Lu, Weifeng He:
A Dual-rail Based Dynamic Voltage and Frequency Scaling for Wide-Voltage-Range Processor. ASICON 2021: 1-4 - [c50]Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok:
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. DAC 2021: 1093-1098 - [c49]Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok:
An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits. ICCAD 2021: 1-9 - [c48]Weijun Zheng, Weiping Shao, Weifeng He, Jian Zhang, Bin Hou, Yong Zhang:
Hierarchical Resource Allocation for RAN slicing in Power Wireless Private Network. ICSPCC 2021: 1-6 - [c47]Tianhong Shen, Yanan Sun, Weifeng He, Zhi Li, Weiyi Liu, Zhezhi He, Li Jiang:
A Ternary Memristive Logic-in-Memory Design for Fast Data Scan. ICTA 2021: 183-184 - [c46]Jieyu Li
Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process. ISCAS 2021: 1-5 - [c45]Weiyi Liu, Yanan Sun, Weifeng He, Qin Wang:
Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars. ISCAS 2021: 1-5 - [c44]Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok:
An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits. ISCAS 2021: 1-5 - [c43]Hao Zhang, Jieyu Li
An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM. ISCAS 2021: 1-5 - [c42]Chao Zhang, Jingtong Mo, Zihan Lian, Weifeng He:
High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory. ISCAS 2021: 1-4 - 2020
- [j18]Jing Wang
Multi-Label Classification of Fundus Images With EfficientNet. IEEE Access 8: 212499-212508 (2020) - [j17]Yanan Sun
Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2431-2441 (2020) - [c41]Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Zhigang Mao, Mingoo Seok:
25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip. ISSCC 2020: 394-396
2010 – 2019
- 2019
- [j16]Yanan Sun
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 753-757 (2019) - [c40]Jiachen Jiang, Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. ASICON 2019: 1-4 - [c39]Yue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jianfei Jiang:
A New Approximate Multiplier Design for Digital Signal Processing. ASICON 2019: 1-4 - [c38]Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. ICEIC 2019: 1-2 - [c37]Joao Pedro Cerqueira, Jieyu Li
A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies. MWSCAS 2019: 1049-1052 - [c36]Yongjie Lu, Yanan Sun, Weifeng He, Zhigang Mao:
A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency. NANOARCH 2019: 1-6 - 2018
- [c35]Pengfei Ji, Jing Gao, Wenyi Xu, Yanan Sun, Weifeng He, Hui Wu:
Electronic-Photonic Integrated Circuit Design and Crosstalk Modeling for a High Density Multi-Lane MZM Array. ISCAS 2018: 1-5 - 2017
- [j15]Wei Jin, Weifeng He, Jianfei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing:
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. Integr. 58: 27-34 (2017) - [j14]Wei Jin, Guanghui He, Weifeng He, Zhigang Mao:
A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. Integr. 59: 206-217 (2017) - [j13]Wei Jin
Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques. IEEE J. Solid State Circuits 52(9): 2475-2487 (2017) - [j12]Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic. Microelectron. J. 62: 12-20 (2017) - [j11]Wei Jin
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1032-1043 (2017) - [c34]Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. ASICON 2017: 908-911 - [c33]Ling Chen, Yanan Sun, Weifeng He:
Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme. ASICON 2017: 916-919 - [c32]Yongming Ding, Wei Jin, Guanghui He, Weifeng He:
Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage. ASICON 2017: 985-988 - [c31]Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li:
A static-placement, dynamic-issue framework for CGRA loop accelerator. DATE 2017: 1348-1353 - [c30]Li Hu, Jiawei Gu, Guanghui He, Weifeng He:
A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications. ISCAS 2017: 1-4 - [c29]Xuwei Jin, Wei Jin, Hao Zhang, Jianfei Jiang, Weifeng He:
A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency. ISCAS 2017: 1-4 - 2016
- [j10]Liang Hong, Wei-Feng He, Guanghui He, Zhigang Mao:
Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding. IEICE Electron. Express 13(6): 20160019 (2016) - [j9]Zhiting Yan, Guanghui He, Weifeng He, Shuaijie Wang, Zhigang Mao:
High performance parallel turbo decoder with configurable interleaving network for LTE application. Integr. 52: 77-90 (2016) - [j8]Jianfei Jiang
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. J. Circuits Syst. Comput. 25(10): 1650121:1-1650121:31 (2016) - [c28]Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok:
A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines. A-SSCC 2016: 129-132 - [c27]Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao:
Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. FPT 2016: 233-236 - 2015
- [j7]Jianfei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao:
Design optimization for capacitive-resistively driven on-chip global interconnect. IEICE Electron. Express 12(8): 20150111 (2015) - [j6]Zhiting Yan, Guanghui He, Weifeng He, Zhigang Mao:
Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(2): 776-782 (2015) - [j5]Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jianfei Jiang, Zhigang Mao:
Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(11): 2706-2717 (2015) - [c26]Fengshuo Tian, Weiguang Sheng, Weifeng He:
An automatic translation and parallelization system for general purpose reconfigurable processor. ASICON 2015: 1-4 - [c25]Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao:
Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. ICCAD 2015: 764-769 - [c24]Zijian Hou, Xin Chen, Weifeng He:
Improved pipeline data flow for DySER-based platform. ISQED 2015: 135-140 - [c23]Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao:
Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig 2015: 1-8 - 2014
- [j4]Zhiting Yan, Guanghui He, Xi Chen, Weifeng He, Zhigang Mao:
Improved Max-Log-MAP BICM-IDD receiver for MIMO systems. IEICE Electron. Express 11(21): 20140800 (2014) - [c22]Ziyou Yao, Weifeng He, Liang Hong, Guanghui He, Zhigang Mao:
Area and throughput efficient IDCT/IDST architecture for HEVC standard. ISCAS 2014: 2511-2514 - 2013
- [j3]Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao:
A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard. IEICE Electron. Express 10(9): 20130210 (2013) - [c21]Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao:
Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. ASICON 2013: 1-4 - [c20]Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao:
A cost effective 2-D adaptive block size IDCT architecture for HEVC standard. MWSCAS 2013: 1290-1293 - 2012
- [j2]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He:
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. 18(1): 13:1-13:18 (2012) - [c19]Weiguang Sheng, Weifeng He, Jianfei Jiang, Zhigang Mao:
Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. IPDPS Workshops 2012: 425-430 - [c18]Jianfei Jiang, Wei-Guang Sheng, Zhi-Gang Mao, Wei-Feng He:
A pre-emphasis circuit design for high speed on-chip global interconnect. ISCAS 2012: 2941-2944 - [c17]Bingjing Ge, Naifeng Jing, Weifeng He, Zhigang Mao:
Contention and energy aware mapping for real-time applications on Network-on-Chip. ISOCC 2012: 72-76 - [c16]Shunqing Yan, Liang Hong, Weifeng He, Qin Wang:
Group-Based Fast Mode Decision Algorithm for Intra Prediction in HEVC. SITIS 2012: 225-229 - 2011
- [c15]Hao Wang, Weiguang Sheng, Weifeng He:
Automatic compilation flow for a coarse-grained reconfigurable processor. ASICON 2011: 687-690 - [c14]Yifan Zhou, Weiguang Sheng, Xie Liu, Weifeng He, Zhigang Mao:
Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm. ASICON 2011: 941-944 - [c13]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He:
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL 2011: 282-285 - [c12]Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He:
Mitigating FPGA interconnect soft errors by in-place LUT inversion. ICCAD 2011: 582-586 - [c11]Yuliang Tao, Guanghui He, Weifeng He, Qin Wang, Jun Ma, Zhigang Mao:
Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems. ISCAS 2011: 1487-1490 - [c10]Li Xie, Weifeng He, Naifeng Jing, Zhigang Mao:
A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor. ISCAS 2011: 1952-1955 - [c9]Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao:
A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. VLSI-SoC 2011: 126-129 - [c8]Naifeng Jing, Weifeng He, Zhigang Mao:
A general statistical estimation for application mapping in Network-on-Chip. VLSI-SoC 2011: 172-175 - [c7]Jianfei Jiang, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao:
A clock-less transceiver for global interconnect. VLSI-SoC 2011: 184-187 - [c6]Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao:
Robust design of sub-threshold flip-flop cells for wireless sensor network. VLSI-SoC 2011: 440-443 - 2010
- [j1]Naifeng Jing, Weifeng He, Yongxin Zhu, Zhigang Mao:
Statistical estimation and evaluation for communication mapping in Network-on-Chip. Integr. 43(2): 220-229 (2010) - [c5]Naifeng Jing, Weifeng He, Zhigang Mao:
Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array. SoCC 2010: 260-265 - [c4]Weifeng He, Weiwei Chen, Zhigang Mao:
An efficient VLSI architecture for extended variable block sizes motion estimation. SoCC 2010: 347-350
2000 – 2009
- 2007
- [c3]Wei-Feng He, Zhi-Gang Mao:
An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation. ISCAS 2007: 1381-1384 - [c2]Wei-Feng He, Meng-Lian Zhao, Chi-Ying Tsui
A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. VLSI Design 2007: 830-835 - 2005
- [c1]Weifeng He, Yunlong Bi, Zhigang Mao:
Efficient frame-level pipelined array architecture for full-search block-matching motion estimation. ISCAS (3) 2005: 2887-2890
Coauthor Index
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