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David Levacq
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2020 – today
- 2024
- [c5]Adem Coskun, Salvatore D'Addio, Richard Jansen, David Levacq, Piero Angeletti:
112-Gbps High Speed Serial Links to Interconnect Direct RF Sampling ADCs and Digital High Throughput Satellite Processors. MeditCom 2024: 431-434
2000 – 2009
- 2008
- [j3]David Levacq, Makoto Takamiya, Takayasu Sakurai:
Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time. IEEE J. Solid State Circuits 43(11): 2390-2395 (2008) - [c4]Yasumi Nakamura, David Levacq, Limin Xiao, Takuya Minakawa, Taro Niiyama, Makoto Takamiya, Takayasu Sakurai:
1/5 power reduction by global optimization based on fine-grained body biasing. CICC 2008: 547-550 - 2007
- [j2]David Levacq, Vincent Dessard, Denis Flandre
:
Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode. IEEE J. Solid State Circuits 42(3): 689-702 (2007) - [j1]David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat:
Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. J. Multiple Valued Log. Soft Comput. 13(1-2): 61-78 (2007) - [c3]David Levacq, Takuya Minakawa, Makoto Takamiya, Takayasu Sakurai:
A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS. CICC 2007: 257-260 - [c2]David Levacq, Muhammad Yazid, Hiroshi Kawaguchi
Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. ESSCIRC 2007: 190-193 - 2005
- [c1]David Levacq, Vincent Dessard, Denis Flandre
Ultra-low power flip-flops for MTCMOS circuits. ISCAS (5) 2005: 4681-4684
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