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Mong-Kai Ku
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2010 – 2019
- 2013
- [j3]Chia-Yu Lin, Shu-Cheng Chou, Mong-Kai Ku:
Operation reduced low-density parity-check decoding algorithms for low power communication systems. Int. J. Commun. Syst. 26(1): 68-83 (2013) - 2011
- [j2]Chia-Yu Lin, Chih-Chun Wei, Mong-Kai Ku:
Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2): 773-780 (2011)
2000 – 2009
- 2009
- [c8]Chia-Yu Lin, Mong-Kai Ku:
Node Operation Reduced Decoding for LDPC Codes. ISCAS 2009: 896-899 - [c7]Chun F. Hsu, Mong-Kai Ku, Li-Yen Liu:
Support vector machine FPGA implementation for video shot boundary detection application. SoCC 2009: 239-242 - 2008
- [c6]Chia-Yu Lin, Chih-Chun Wei, Mong-Kai Ku:
Efficient encoding for dual-diagonal structured LDPC codes based on parity bit prediction and correction. APCCAS 2008: 1648-1651 - [c5]Shu-Cheng Chou, Mong-Kai Ku, Chia-Yu Lin:
Switching activity reducing layered decoding algorithm for LDPC codes. ISCAS 2008: 528-531 - [c4]Chia-Yu Lin, Mong-Kai Ku, Yi-Hsing Chien:
Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism. VTC Spring 2008: 1423-1427 - 2007
- [c3]Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen:
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME 2007: 9 - [c2]Yi-Hsing Chien, Mong-Kai Ku:
A High Throughput H-QC LDPC Decoder. ISCAS 2007: 1649-1652 - 2005
- [c1]Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen:
Reconfigurable Platform for Content Science Research. RTCSA 2005: 481-486
1990 – 1999
- 1999
- [j1]Alan Y. Kwentus, Patrick Pai, Steven Jaffe, Ray Gomez, Shauhyuarn Sean Tsai, Tom Kwan, Hing T. Hung, Young J. Shin, Vin Hue, Darwin Cheung, Raheel A. Khan, Christopher M. Ward, Mong-Kai Ku, Kenneth Choi, Jim Searle, Klaas Bult, Kelly B. Cameron, Jason Demas, Charles Reames, Henry Samueli:
A single-chip universal digital satellite receiver with 480-MHz IF input. IEEE J. Solid State Circuits 34(11): 1634-1646 (1999)
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