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Alexander Finder
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2010 – 2019
- 2016
- [j3]Jan Malburg, Alexander Finder, Görschwin Fey
:
Debugging hardware designs using dynamic dependency graphs. Microprocess. Microsystems 47: 347-359 (2016) - 2014
- [j2]Alexander Finder, André Sülflow, Görschwin Fey
Latency Analysis for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 643-647 (2014) - [j1]Jan Malburg, Alexander Finder, Görschwin Fey
A Simulation-Based Approach for Automated Feature Localization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1886-1899 (2014) - 2013
- [c9]Jan Malburg, Alexander Finder, Görschwin Fey:
Tuning dynamic data flow analysis to support design understanding. DATE 2013: 1179-1184 - [c8]Alexander Finder, Jan-Philipp Witte, Görschwin Fey
Debugging HDL designs based on functional equivalences with high-level specifications. DDECS 2013: 60-65 - 2012
- [c7]Jan Malburg, Alexander Finder, Görschwin Fey
Automated feature localization for hardware designs using coverage metrics. DAC 2012: 941-946 - [c6]Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow:
FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference 2012: 260-265 - [c5]Jan Malburg, Alexander Finder, Görschwin Fey:
Automated Feature Localization for Hardware Designs using Coverage Metrics. MBMV 2012: 85-96 - 2011
- [c4]Alexander Finder, André Sülflow, Görschwin Fey
Latency Analysis for Sequential Circuits. ETS 2011: 129-134 - [c3]Rolf Drechsler
Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms. EvoApplications (2) 2011: 151-161 - 2010
- [c2]Alexander Finder, Görschwin Fey:
Evaluating Debugging Algorithms from a Qualitative Perspective. FDL 2010: 37-42 - [c1]Alexander Finder, Rolf Drechsler
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions. ISMVL 2010: 150-155
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