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Matthew Naylor
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2020 – today
- 2024
- [j9]Alexandre Joannou, Peter Rugg, Jonathan Woodruff
, Franz A. Fuchs
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection. IEEE Des. Test 41(1): 40-49 (2024) - 2023
- [j8]Andrew D. Brown
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. ACM Trans. Parallel Comput. 10(2): 7:1-7:32 (2023) - 2022
- [j7]Ashur Rafiev
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. IET Comput. Digit. Tech. 16(2-3): 71-88 (2022) - [j6]Ashur Rafiev
Practical Distributed Implementation of Very Large Scale Petri Net Simulations. Trans. Petri Nets Other Model. Concurr. 16: 112-139 (2022) - 2021
- [c20]Matthew Naylor, Simon W. Moore, David B. Thomas
General hardware multicasting for fine-grained message-passing architectures. PDP 2021: 126-133 - 2020
- [j5]Matthew Naylor
A Scoping Review Identifying the Need for Quality Research on the Use of Virtual Reality in Workplace Settings for Stress Management. Cyberpsychology Behav. Soc. Netw. 23(8): 506-518 (2020) - [c19]Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas
Termination detection for fine-grained message-passing architectures. ASAP 2020: 17-24 - [c18]Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell
Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. SP 2020: 1003-1020
2010 – 2019
- 2019
- [j4]Matthew Naylor
Augmented Experiences: Investigating the Feasibility of Virtual Reality as Part of a Workplace Wellbeing Intervention. Interact. Comput. 31(5): 507-523 (2019) - [c17]Matthew Naylor, Simon W. Moore, David B. Thomas:
Tinsel: A Manythread Overlay for FPGA Clusters. FPL 2019: 375-383 - [c16]Andrew D. Brown, Mark Vousden, Alex Rast, Graeme M. Bragg, David B. Thomas, Jonny Beaumont, Matthew Naylor, Andrey Mokhov:
POETS: Distributed Event-Based Computing - Scaling Behaviour. PARCO 2019: 487-496 - 2017
- [c15]Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas
Programming Model to Develop Supercomputer Combinatorial Solvers. ICPP Workshops 2017: 171-179 - [c14]Andrew D. Brown, David B. Thomas, Jeff Reeve, Ghaith Tarawneh, Alessandro de Gennaro, Andrey Mokhov, Matthew Naylor, Tom Kazmierski:
Distributed Event-Based Computing. PARCO 2017: 583-592 - 2016
- [c13]Matthew Naylor, Simon W. Moore, Alan Mujumdar:
A consistency checker for memory subsystem traces. FMCAD 2016: 133-140 - 2015
- [c12]Matthew Naylor, Simon W. Moore:
A generic synthesisable test bench. MEMOCODE 2015: 128-137 - 2014
- [j3]James Mistry, Matthew Naylor, Jim Woodcock
Adapting FreeRTOS for multicores: an experience report. Softw. Pract. Exp. 44(9): 1129-1154 (2014) - [c11]Matthew Naylor, Simon W. Moore
Rapid codesign of a soft vector processor and its compiler. FPL 2014: 1-4 - 2013
- [c10]Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore
A spiking neural network on a portable FPGA tablet. FPL 2013: 1 - [c9]Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore
Managing the FPGA memory wall: Custom computing or vector processing? FPL 2013: 1-6 - 2012
- [j2]Matthew Naylor, Colin Runciman:
The Reduceron reconfigured and re-evaluated. J. Funct. Program. 22(4-5): 574-613 (2012) - [c8]Jason S. Reich, Matthew Naylor, Colin Runciman:
Advances in Lazy SmallCheck. IFL 2012: 53-70 - 2011
- [c7]Jason S. Reich, Matthew Naylor, Colin Runciman:
Lazy Generation of Canonical Test Programs. IFL 2011: 69-84 - 2010
- [c6]Matthew Naylor, Colin Runciman:
The reduceron reconfigured. ICFP 2010: 75-86
2000 – 2009
- 2009
- [j1]Matthew Naylor, Colin Runciman:
Expressible sharing for functional circuit description. High. Order Symb. Comput. 22(1): 67-80 (2009) - 2008
- [c5]Colin Runciman, Matthew Naylor, Fredrik Lindblad:
Smallcheck and lazy smallcheck: automatic exhaustive testing for small values. Haskell 2008: 37-48 - 2007
- [c4]Matthew Naylor, Emil Axelsson, Colin Runciman:
A functional-logic library for wired. Haskell 2007: 37-48 - [c3]Matthew Naylor, Colin Runciman:
The Reduceron: Widening the von Neumann Bottleneck for Graph Reduction Using an FPGA. IFL 2007: 129-146 - [c2]Matthew Naylor, Colin Runciman:
Finding Inputs that Reach a Target Expression. SCAM 2007: 133-142 - 2005
- [c1]Peter Pakulski, Karl Sammut, Fangpo He, Matthew Naylor:
Pixel Behaviour Metrics for Dynamic Background Modelling with the Projected Difference Pattern Method. DICTA 2005: 25
Coauthor Index
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last updated on 2024-11-13 23:53 CET by the dblp team
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