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Wen-Tsao Chen
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2010 – 2019
- 2012
- [c7]Kuang-Ren Chen, Chia-Ming Tsai, Sheng-Kai You, An-Siou Li, Wen-Tsao Chen:
A 10 Gb/s adaptive cable equalizer using phase detection technique in 0.13µm CMOS technology. ISCAS 2012: 1947-1950 - [c6]Hsu-Che Nee, Chia-Ming Tsai, Sheng-Kai You, Wen-Tsao Chen:
A 6Gb/s adaptive equalizer using overshoot control in 0.18µm CMOS technology. ISCAS 2012: 1963-1966 - 2011
- [j1]Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu
:
SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. IEEE J. Solid State Circuits 46(8): 1893-1903 (2011) - 2010
- [c5]Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. CICC 2010: 1-4
2000 – 2009
- 2009
- [c4]Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu
A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. ISSCC 2009: 82-83 - [c3]Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee:
Subharmonically injection-locked PLLs for ultra-low-noise clock generation. ISSCC 2009: 92-93 - 2008
- [c2]Chung-Wei Lin, Yung-Pin Lee, Wen-Tsao Chen:
A 1.5 bit 5th order CT/DT delta sigma class D amplifier with power efficiency improvement. ISCAS 2008: 280-283 - 2007
- [c1]Chia-Ming Tsai, Wen-Tsao Chen:
A 40mW 3.5kΩ 3Gb/s CMOS Differential Transimpedance Amplifier Using Negative-Impedance Compensation. ISSCC 2007: 52-586
Coauthor Index
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