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Chi-Feng Wu
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2010 – 2019
- 2017
- [c16]Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu:
Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. VLSI-DAT 2017: 1-4 - 2014
- [c15]Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang:
Mask-cost-aware ECO routing∗. DATE 2014: 1-4 - [c14]Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu:
Apply high-level synthesis design and verification methodology on floating-point unit implementation. VLSI-DAT 2014: 1-4 - 2013
- [c13]Pei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu:
Case study of yield learning through in-house flow of volume diagnosis. VLSI-DAT 2013: 1-4 - 2012
- [j13]Shiueng-Bien Yang, Chi-Feng Wu:
Locating Text in Images Based on the Smooth Gray-Level Detection. Int. J. Image Graph. 12(4) (2012) - [j12]Chi-Feng Wu, Cheng-Jian Lin, Chi-Yung Lee:
Applying a Functional Neurofuzzy Network to Real-Time Lane Detection and Front-Vehicle Distance Measurement. IEEE Trans. Syst. Man Cybern. Part C 42(4): 577-589 (2012) - [c12]Chih-Wea Wang, Chen-Tung Lin, Chun-Chieh Hsu, Ching-Tung Wu, Chi-Feng Wu:
Test for more than pass/fail using on-chip temperature sensor. VLSI-DAT 2012: 1-4 - 2011
- [j11]Chi-Feng Wu, Cheng-Jian Lin, Chi-Yung Lee:
A functional neural fuzzy network for classification applications. Expert Syst. Appl. 38(5): 6202-6208 (2011)
2000 – 2009
- 2009
- [j10]Chenn-Jung Huang
, You-Jia Chen, Chi-Feng Wu, Yi-An Huang:
Application of neural networks and genetic algorithms to the screening for high quality chips. Appl. Soft Comput. 9(2): 824-832 (2009) - [c11]Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu:
A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. ITC 2009: 1-10 - 2007
- [c10]Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu:
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs. ATS 2007: 355-360 - 2004
- [j9]Hsiao-Hwa Chen, Chi-Feng Wu:
A novel approach to enable decorrelating multiuser detection without matrix inversion operations. Int. J. Commun. Syst. 17(9): 851-871 (2004) - 2003
- [j8]Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
Built-in redundancy analysis for memory yield improvement. IEEE Trans. Reliab. 52(4): 386-399 (2003) - [j7]Hsiao-Hwa Chen, Jin-Xiao Lin, Shin-Wei Chu, Chi-Feng Wu, Guo-Sheng Chen:
Isotropic air-interface technologies for fourth generation wireless communications. Wirel. Commun. Mob. Comput. 3(6): 687-704 (2003) - 2002
- [j6]Chenn-Jung Huang
Image Processing Techniques for Wafer Defect Cluster Identification. IEEE Des. Test Comput. 19(2): 44-48 (2002) - [j5]Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. J. Electron. Test. 18(6): 637-647 (2002) - [j4]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 480-490 (2002) - [c9]Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA 2002: 137-141 - 2001
- [c8]Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang:
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103- - [c7]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC 2001: 301-306 - 2000
- [j3]Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao:
Single-ended SRAM with high test coverage and short test time. IEEE J. Solid State Circuits 35(1): 114-118 (2000) - [j2]Chi-Feng Wu, Cheng-Wen Wu
Testing and Diagnosing Dynamic Reconfigurable FPGA. VLSI Design 10(3): 321-333 (2000) - [c6]Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu:
Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17 - [c5]Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin:
A built-in self-test and self-diagnosis scheme for embedded SRAM. Asian Test Symposium 2000: 45-50 - [c4]Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD 2000: 468-471 - [c3]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation for Random Access Memories. VTS 2000: 291-296
1990 – 1999
- 1999
- [j1]Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu
A Programmable BIST Core for Embedded DRAM. IEEE Des. Test Comput. 16(1): 59-70 (1999) - [c2]Chi-Feng Wu, Cheng-Wen Wu
Testing Interconnects of Dynamic Reconfigurable FPGAs. ASP-DAC 1999: 279-282 - [c1]Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
RAMSES: A Fast Memory Fault Simulator. DFT 1999: 165-173
Coauthor Index
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