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Yao Chen 0008
Person information
- affiliation: Advanced Digital Sciences Center, Illinois at Singapore, Singapore
Other persons with the same name
- Yao Chen — disambiguation page
- Yao Chen 0001 — University of Massachusetts at Lowell, Manning School of Business, MA, USA
- Yao Chen 0002 — Stevens Institute of Technology, Wireless Research Lab, Hoboken, NJ, USA
- Yao Chen 0003
— Southwestern University of Finance and Economics, Department of Computer Science, Chengdu, China (and 3 more)
- Yao Chen 0004
- Yao Chen 0005
- Yao Chen 0006
- Yao Chen 0007
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2020 – today
- 2024
- [j12]Kunpeng Xie
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs. ACM Trans. Archit. Code Optim. 21(2): 31 (2024) - [c27]Cheng Gong, Yao Chen, Qiuyang Luo, Ye Lu, Tao Li, Yuzhi Zhang, Yufei Sun, Le Zhang:
Deep Feature Surgery: Towards Accurate and Efficient Multi-exit Networks. ECCV (49) 2024: 435-451 - [i24]Daisuke Mashima, Yao Chen, Muhammad M. Roomi, Subhash Lakshminarayana, Deming Chen:
Cybersecurity for Modern Smart Grid against Emerging Threats. CoRR abs/2404.04466 (2024) - [i23]Cheng Gong, Yao Chen, Qiuyang Luo, Ye Lu, Tao Li, Yuzhi Zhang, Yufei Sun, Le Zhang:
Deep Feature Surgery: Towards Accurate and Efficient Multi-Exit Networks. CoRR abs/2407.13986 (2024) - [i22]Zining Zhang, Yao Chen, Bingsheng He, Zhenjie Zhang:
Aggressive Post-Training Compression on Extremely Large Language Models. CoRR abs/2409.20094 (2024) - 2023
- [j11]Daisuke Mashima, Yao Chen, Muhammad M. Roomi, Subhash Lakshminarayana, Deming Chen:
Cybersecurity for Modern Smart Grid Against Emerging Threats. Found. Trends Priv. Secur. 5(4): 189-285 (2023) - [j10]Hongshi Tan
LightRW: FPGA Accelerated Graph Dynamic Random Walks. Proc. ACM Manag. Data 1(1): 90:1-90:27 (2023) - [j9]Qiange Wang
HongTu: Scalable Full-Graph GNN Training on Multiple GPUs. Proc. ACM Manag. Data 1(4): 246:1-246:27 (2023) - [j8]Zining Zhang
NIOT: A Novel Inference Optimization of Transformers on Modern CPUs. IEEE Trans. Parallel Distributed Syst. 34(6): 1982-1995 (2023) - [i21]Hongshi Tan, Xinyu Chen, Yao Chen, Bingsheng He, Weng-Fai Wong:
LightRW: FPGA Accelerated Graph Dynamic Random Walks. CoRR abs/2304.07004 (2023) - [i20]Qiange Wang, Yao Chen, Weng-Fai Wong, Bingsheng He:
HongTu: Scalable Full-Graph GNN Training on Multiple GPUs (via communication-optimized CPU data offloading). CoRR abs/2311.14898 (2023) - 2022
- [j7]Xinyu Chen, Feng Cheng, Hongshi Tan, Yao Chen
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS. ACM Trans. Reconfigurable Technol. Syst. 15(4): 44:1-44:31 (2022) - [c26]Xinheng Liu, Yao Chen
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation. ASP-DAC 2022: 140-146 - [c25]Xinyu Chen, Yao Chen, Feng Cheng, Hongshi Tan, Bingsheng He, Weng-Fai Wong
ReGraph: Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines. MICRO 2022: 1342-1358 - [c24]Prakhar Ganesh, Yao Chen, Yin Yang, Deming Chen, Marianne Winslett:
YOLO-ReT: Towards High Accuracy Real-time Object Detection on Edge GPUs. WACV 2022: 1311-1321 - [i19]Xinyu Chen, Yao Chen, Feng Cheng, Hongshi Tan, Bingsheng He, Weng-Fai Wong:
ReGraph: Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines. CoRR abs/2203.02676 (2022) - [i18]Xiaofan Zhang, Yao Chen, Cong Hao, Sitao Huang, Yuhong Li, Deming Chen:
Efficient Machine Learning, Compilers, and Optimizations for Embedded Systems. CoRR abs/2206.03326 (2022) - [i17]Yao Chen, Junhao Pan, Xinheng Liu, Jinjun Xiong
HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation. CoRR abs/2208.00763 (2022) - 2021
- [j6]Prakhar Ganesh, Yao Chen, Xin Lou, Mohammad Ali Khan, Yin Yang, Hassan Sajjad
Compressing Large-Scale Transformer-Based Models: A Case Study on BERT. Trans. Assoc. Comput. Linguistics 9: 1061-1080 (2021) - [j5]Cheng Gong
VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization. IEEE Trans. Computers 70(5): 696-710 (2021) - [j4]Prakhar Ganesh
Learning-Based Simultaneous Detection and Characterization of Time Delay Attack in Cyber-Physical Systems. IEEE Trans. Smart Grid 12(4): 3581-3593 (2021) - [c23]Xinheng Liu, Yao Chen
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs. ASAP 2021: 258-265 - [c22]Lixiang Li, Yao Chen
MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank. DAC 2021: 601-606 - [c21]Xinyu Chen, Hongshi Tan, Yao Chen
Skew-Oblivious Data Routing for Data Intensive Applications on FPGAs with HLS. DAC 2021: 937-942 - [c20]Xinyu Chen, Hongshi Tan, Yao Chen
ThunderGP: HLS-based Graph Processing Framework on FPGAs. FPGA 2021: 69-80 - [c19]Yao Chen
3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low Bitwidth Quantization, and Ultra-Low Latency Acceleration. ACM Great Lakes Symposium on VLSI 2021: 157-162 - [c18]Hongshi Tan, Xinyu Chen, Yao Chen
ThundeRiNG: generating multiple independent random number sequences on FPGAs. ICS 2021: 115-126 - [i16]Lixiang Li, Yao Chen, Zacharie Zirnheld, Pan Li, Cong Hao:
MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank. CoRR abs/2104.09616 (2021) - [i15]Xinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, Deming Chen:
Skew-Oblivious Data Routing for Data-Intensive Applications on FPGAs with HLS. CoRR abs/2105.04151 (2021) - [i14]Yao Chen, Cole Hawkins, Kaiqi Zhang, Zheng Zhang, Cong Hao:
3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low BitwidthQuantization, and Ultra-Low Latency Acceleration. CoRR abs/2105.06250 (2021) - [i13]Hongshi Tan, Xinyu Chen, Yao Chen, Bingsheng He, Weng-Fai Wong:
ThundeRiNG: Generating Multiple Independent Random Number Sequences on FPGAs. CoRR abs/2105.09578 (2021) - [i12]Xinheng Liu, Yao Chen, Cong Hao, Ashutosh Dhar, Deming Chen:
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs. CoRR abs/2107.04244 (2021) - [i11]Lingdong Kong, Prakhar Ganesh, Tan Wang, Junhao Liu, Yao Chen, Le Zhang:
Free Lunch for Co-Saliency Detection: Context Adjustment. CoRR abs/2108.02093 (2021) - [i10]Prakhar Ganesh, Yao Chen, Yin Yang, Deming Chen, Marianne Winslett:
YOLO-ReT: Towards High Accuracy Real-time Object Detection on Edge GPUs. CoRR abs/2110.13713 (2021) - [i9]Xinheng Liu, Yao Chen, Prakhar Ganesh, Junhao Pan, Jinjun Xiong, Deming Chen:
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation. CoRR abs/2112.13972 (2021) - 2020
- [c17]Ruichu Cai, Zhihao Liang, Boyan Xu, Zijian Li, Yuexing Hao, Yao Chen
TAG : Type Auxiliary Guiding for Code Comment Generation. ACL 2020: 291-301 - [c16]Xinyu Chen, Yao Chen, Ronak Bajaj, Jiong He, Bingsheng He, Weng-Fai Wong, Deming Chen:
Is FPGA Useful for Hash Joins? CIDR 2020 - [c15]Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions. DAC 2020: 1-6 - [c14]Cong Hao, Yao Chen
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices. ACM Great Lakes Symposium on VLSI 2020: 283-290 - [c13]Yao Chen
HaoCL: Harnessing Large-scale Heterogeneous Processors Made Easy. ICDCS 2020: 1231-1234 - [i8]Prakhar Ganesh
Compressing Large-Scale Transformer-Based Models: A Case Study on BERT. CoRR abs/2002.11985 (2020) - [i7]Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen, Jinjun Xiong, Wen-Mei W. Hwu, Deming Chen:
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions. CoRR abs/2005.02563 (2020) - [i6]Ruichu Cai, Zhihao Liang, Boyan Xu, Zijian Li, Yuexing Hao, Yao Chen:
TAG : Type Auxiliary Guiding for Code Comment Generation. CoRR abs/2005.02835 (2020) - [i5]Yao Chen, Xin Long, Jiong He, Yuhang Chen, Hongshi Tan, Zhenxiang Zhang, Marianne Winslett, Deming Chen:
HaoCL: Harnessing Large-scale Heterogeneous Processors Made Easy. CoRR abs/2005.08466 (2020) - [i4]Cheng Gong, Yao Chen, Ye Lu, Tao Li, Cong Hao, Deming Chen:
VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization. CoRR abs/2005.08501 (2020) - [i3]Cong Hao, Yao Chen, Xiaofan Zhang, Yuhong Li, Jinjun Xiong, Wen-Mei Hwu, Deming Chen:
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices. CoRR abs/2010.07185 (2020)
2010 – 2019
- 2019
- [c12]Yao Chen
Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs. FPGA 2019: 73-82 - [c11]Xinyu Chen, Ronak Bajaj, Yao Chen
On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL-Based FPGAs. FPL 2019: 67-73 - [c10]Cong Hao, Yao Chen
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving. ICCAD 2019: 1-8 - [c9]Cheng Gong
µL2Q: An Ultra-Low Loss Quantization Method for DNN Compression. IJCNN 2019: 1-8 - [c8]Huachao Xu, Jinlong Hu, Yao Chen
Pico-Ampere Voltage References for IoT Systems. ISCAS 2019: 1-5 - [c7]Yao Chen
T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA. ISVLSI 2019: 13-18 - [i2]Xiaofan Zhang, Cong Hao, Yuhong Li, Yao Chen
A Bi-Directional Co-Design Approach to Enable Deep Learning on IoT Devices. CoRR abs/1905.08369 (2019) - [i1]Cong Hao, Yao Chen, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong, Wen-Mei Hwu, Junli Gu, Deming Chen:
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving. CoRR abs/1911.07446 (2019) - 2018
- [j3]Jihe Wang
A locality-aware shuffle optimization on fat-tree data centers. Future Gener. Comput. Syst. 89: 31-43 (2018) - [c6]Yao Chen
HASS: High Accuracy Spike Sorting with Wavelet Package Decomposition and Mutual Information. BIBM 2018: 831-838 - [c5]Jiong He, Yao Chen
HaaS: Cloud-Based Real-Time Data Analytics with Heterogeneity-Aware Scheduling. ICDCS 2018: 1017-1028 - 2016
- [j2]Ying Chen, Tan Nguyen, Yao Chen
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2032-2045 (2016) - [j1]Yao Chen
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2220-2233 (2016) - [c4]Xinheng Liu, Yao Chen
High Level Synthesis of Complex Applications: An H.264 Video Decoder. FPGA 2016: 224-233 - [c3]Tan Nguyen, Yao Chen
SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow. ISVLSI 2016: 661-666 - 2015
- [c2]Liwei Yang, Yao Chen
System-level design solutions: Enabling the IoT explosion. ASICON 2015: 1-4 - 2014
- [c1]Swathi T. Gurumani, Jacob Tolar, Yao Chen
Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. FCCM 2014: 21-24
Coauthor Index
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last updated on 2024-11-15 19:35 CET by the dblp team
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