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Scott Kaylor
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2010 – 2019
- 2016
- [c3]Nikolaus Klemmer, S. Akhtar, V. Srinivasan, P. Litmanen, Himanshu Arora, Satish Uppathil, Scott Kaylor, A. Akour, V. Wang, M. Fares, F. Dulger, A. Frank, D. Ghosh, S. Madhavapeddi, H. Safiri, J. Mehta, A. Jain, H. Choo, E. Zhang, Charles K. Sestok, C. Fernando, Rajagopal K. A., S. Ramakrishnan, V. Sinari, V. Baireddy:
9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth. ISSCC 2016: 164-165 - [c2]Vishnu Ravinuthula, William Bright, Mark Weaver, Kenneth Maclean, Scott Kaylor, Sidharth Balasubramanian, Jesse Coulon, Robert Keller, Bao Nguyen, Ebenezer Dwobeng:
A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz. VLSI Circuits 2016: 1-2 - 2014
- [j3]Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Kenneth Maclean, Jake Hu, Mark Weaver, Matthew Gindlesperger, Scott Kaylor, Robert Payne, Charles K. Sestok, William Bright:
A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC. IEEE J. Solid State Circuits 49(9): 1876-1885 (2014) - 2010
- [j2]Robert Payne, Marco Corsi, David Smith, Tien-Ling Hsieh, Scott Kaylor:
A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR. IEEE J. Solid State Circuits 45(12): 2613-2622 (2010) - [c1]Robert Payne, Marco Corsi, David Smith, Scott Kaylor, Daniel Hsieh:
A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR. ISSCC 2010: 294-295
1990 – 1999
- 1996
- [j1]Kavch Parsi, Robert P. Burns, Alan Chaiken, Mark Chambers, William R. Forni, David Harnishfeger, Scott Kaylor, Micheal J. Pennell, Jose O. Perez, Narendra Rao, Mark Rohrhaugh, Mike Ross, Gary L. Stuhlmiller:
A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD. IEEE J. Solid State Circuits 31(11): 1817-1830 (1996)
Coauthor Index
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