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2020 – today
- 2023
- [j4]Stefano Ambrogio, Pritish Narayanan, Atsuya Okazaki
, Andrea Fasoli, Charles Mackin
An analog-AI chip for energy-efficient speech recognition and transcription. Nat. 620(7975): 768-775 (2023) - [i3]Julian Büchel, Athanasios Vasilopoulos, Benedikt Kersting, Frédéric Odermatt, Kevin Brew, Injo Ok, Samuel Choi, Iqbal Saraf, Victor Chan, Timothy Philip, Nicole Saulnier, Vijay Narayanan, Manuel Le Gallo, Abu Sebastian:
Gradient descent-based programming of analog in-memory computing cores. CoRR abs/2305.16647 (2023) - 2022
- [j3]Jin-Ping Han
Impact of Phase-Change Memory Flicker Noise and Weight Drift on Analog Hardware Inference for Large-Scale Deep Learning Networks. Adv. Intell. Syst. 4(5) (2022) - [j2]Riduan Khaddam-Aljameh
HERMES-Core - A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs. IEEE J. Solid State Circuits 57(4): 1027-1038 (2022) - [c3]Geethan Karunaratne, Michael Hersche, Jovin Langenegger, Giovanni Cherubini, Manuel Le Gallo, Urs Egger, Kevin Brew, Samuel Choi, Injo Ok, Mary Claire Silvestre, Ning Li, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan
In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory. ESSCIRC 2022: 105-108 - [i2]Geethan Karunaratne, Michael Hersche, Jovin Langenegger, Giovanni Cherubini, Manuel Le Gallo, Urs Egger, Kevin Brew, Samuel Choi, Injo Ok, Mary Claire Silvestre, Ning Li, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan
In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory. CoRR abs/2207.06810 (2022) - [i1]Manuel Le Gallo, Riduan Khaddam-Aljameh, Milos Stanisavljevic, Athanasios Vasilopoulos, Benedikt Kersting, Martino Dazzi, Geethan Karunaratne, Matthias Braendli
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. CoRR abs/2212.02872 (2022) - 2021
- [c2]Robert L. Bruce, Syed Ghazi Sarwat
Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation. IRPS 2021: 1-6 - [c1]Riduan Khaddam-Aljameh, Milos Stanisavljevic, Jordi Fornt Mas
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing. VLSI Circuits 2021: 1-2
2010 – 2019
- 2011
- [j1]Jungwoo Oh
High Transport Si/SiGe Heterostructures for CMOS Transistors with Orientation and Strain Enhanced Mobility. IEICE Trans. Electron. 94-C(5): 712-716 (2011)
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