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Tong-Yu Hsieh
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2020 – today
- 2024
- [c31]Jun-Tsung Wu, Hideyuki Ichihara, Tomoo Inoue, Tong-Yu Hsieh:
On Accuracy Enhancement of No-Reference Error-Tolerability Testing for Images in Object Detection Applications Based on RGB Channel Characteristics. ITC-Asia 2024: 1-6 - 2023
- [j18]Tong-Yu Hsieh, Chun-Chao Cheng, Wei-Ji Chao, Pin-Xuan Wu:
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1323-1335 (2023) - [c30]Wei-Ji Chao, Tong-Yu Hsieh:
Cost-Effective Error-Mitigation for High Memory Error Rate of DNN: A Case Study on YOLOv4. ITC-Asia 2023: 1-6 - 2022
- [c29]Tong-Yu Hsieh, Pao-Wei Tsui, Jun-Tsung Wu:
On No-Reference Error Detection of an Image Stitching System Based on Error-Tolerance. ATS 2022: 150-155 - 2021
- [c28]Tong-Yu Hsieh, Jun-Tsung Wu:
Investigation on Error-Tolerability Enhancement of Videos via Re-Encoding for Computer Vision: A Case Study on Object Detection. ICCE-TW 2021: 1-2 - [c27]Chih-Hao Wang, Natalia Lylina, Ahmed Atteya, Tong-Yu Hsieh, Hans-Joachim Wunderlich:
Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems. IOLTS 2021: 1-7 - 2020
- [j17]Chih-Hao Wang, Tong-Yu Hsieh:
An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications. ACM Trans. Design Autom. Electr. Syst. 25(1): 3:1-3:27 (2020) - [c26]Tong-Yu Hsieh, Chen-Chia Chung, Jun-Tsung Wu:
On Enhancing Error-Tolerability of Videos via Re-Encoding with Adaptive I-Frame Insertion. ITC-Asia 2020: 136-141 - [c25]Tong-Yu Hsieh, Yu-Min Chung:
A Self-Detection and Self-Repair Methodology for Reliable Speech Recognition Considering AWGN Noises. ITC-Asia 2020: 142-147 - [c24]Tong-Yu Hsieh, Hsin-Yung Shen, Chia-Teng Hsu:
Cost-Effective Reliable Edge Computing Hardware Design Based on Module Simplification and Duplication: A Case Study on Vehicle Detection Based on Support Vector Machine. VLSI-DAT 2020: 1-4 - [c23]Tong-Yu Hsieh, Pin-Xuan Wu, Chun-Chao Cheng:
On Classification of Acceptable Images for Reliable Artificial Intelligence Systems: A Case Study on Pedestrian Detection. VTS 2020: 1-6
2010 – 2019
- 2019
- [c22]Tong-Yu Hsieh, Yuan-Cheng Lin, Hsin-Yung Shen:
On Automatic Generation of Training Images for Machine Learning in Automotive Applications. AICAS 2019: 225-228 - [c21]Tong-Yu Hsieh, Kuang-Chun Lin, Hsin-Hsien Lin:
A Delay-Aware Implementation Scheme for Cost-Effective Implication-Based Concurrent Error Detection. ITC-Asia 2019: 145-150 - 2018
- [j16]Tong-Yu Hsieh, Yi-Han Peng, Kuan-Chih Cheng:
Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 485-498 (2018) - [j15]Chih-Hao Wang, Tong-Yu Hsieh:
On Probability of Detection Lossless Concurrent Error Detection Based on Implications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1090-1103 (2018) - [c20]Tong-Yu Hsieh, Shang-En Chan, Chi-Hsuan Ho:
On no-reference on-line error-tolerability testing for videos. ETS 2018: 1-2 - [c19]Chih-Hao Wang, Chi-Hsuan Ho, Tong-Yu Hsieh:
Error Indication Signal Collapsing for Implication-Based Concurrent Error Detection. ITC-Asia 2018: 127-132 - [c18]Tong-Yu Hsieh, Chao-Ru Chen:
A No-Reference Error-Tolerability Test Methodology for Image Processing Applications. ITC-Asia 2018: 133-138 - 2017
- [j14]Tong-Yu Hsieh, Kuan-Hsien Li, Chen-Chia Chung:
A fault-analysis oriented re-design and cost-effectiveness evaluation methodology for error tolerant applications. Microelectron. J. 66: 48-57 (2017) - [j13]Tong-Yu Hsieh, Tsung-Liang Chih, Mei-Jung Wu:
Cost-Effective Enhancement on Both Yield and Reliability for Cache Designs Based on Performance Degradation Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2434-2448 (2017) - [c17]Tong-Yu Hsieh, Tai-Ang Cheng, Chao-Ru Chen:
Error-Tolerability Evaluation and Test for Images in Face Detection Applications. ATS 2017: 206-211 - [c16]Chih-Hao Wang, Tong-Yu Hsieh:
A hybrid concurrent error detection scheme for simultaneous improvement on probability of detection and diagnosability. ITC-Asia 2017: 52-57 - 2016
- [j12]Tong-Yu Hsieh, Tai-Ping Wang, Shuo Yang, Chin-An Hsu, Yi-Lung Lin:
An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing. IEICE Trans. Electron. 99-C(3): 404-414 (2016) - [j11]Tong-Yu Hsieh, Chih-Hao Wang, Tsung-Liang Chih, Ya-Hsiu Chi:
A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 784-788 (2016) - 2015
- [j10]Tong-Yu Hsieh, Chih-Hao Wang, Chun-Wei Kuo, Shu-Yu Huang, Tsung-Liang Chih:
Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement. J. Electron. Test. 31(5-6): 427-441 (2015) - [c15]Tong-Yu Hsieh, Yi-Han Peng:
Filtering-based error-tolerability evaluation of image processing circuits. IOLTS 2015: 132-137 - 2014
- [j9]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty:
Efficient LFSR Reseeding Based on Internal-Response Feedback. J. Electron. Test. 30(6): 673-685 (2014) - [j8]Tong-Yu Hsieh, Yi-Han Peng, Kuan-Hsien Li:
Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation. J. Electron. Test. 30(6): 687-699 (2014) - [c14]Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh:
Output-bit selection with X-avoidance using multiple counters for test-response compaction. ETS 2014: 1-6 - [c13]Tong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng:
On efficient error-tolerability evaluation and maximization for image processing applications. VLSI-DAT 2014: 1-4 - [c12]Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh:
Output selection for test response compaction based on multiple counters. VLSI-DAT 2014: 1-4 - 2013
- [j7]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty, Yu-Hua Wu:
Counter-Based Output Selection for Test Response Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 152-164 (2013) - [j6]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Wee-Lung Ang:
An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1254-1264 (2013) - [c11]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty:
A New LFSR Reseeding Scheme via Internal Response Feedback. Asian Test Symposium 2013: 97-102 - [c10]Tong-Yu Hsieh, Yi-Han Peng, Chia-Chi Ku:
An Efficient Test Methodology for Image Processing Applications Based on Error-Tolerance. Asian Test Symposium 2013: 289-294 - 2012
- [j5]Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer:
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 754-764 (2012) - [c9]Tong-Yu Hsieh, Chia-Chi Ku, Chia-Hung Yeh:
A yield and reliability enhancement framework for image processing applications. APCCAS 2012: 683-686 - [c8]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh:
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume. Asian Test Symposium 2012: 278-283 - [c7]Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Shih-Shiun Chien, Krishnendu Chakrabarty:
Accumulator-based output selection for test response compaction. ISCAS 2012: 2313-2316 - [c6]Wei-Cheng Lien, Tong-Yu Hsieh, Kuen-Jong Lee:
Routing-efficient implementation of an internal-response-based BIST architecture. VLSI-DAT 2012: 1-4 - 2011
- [j4]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 930-934 (2011) - [j3]Kuen-Jong Lee, Wei-Cheng Lien, Tong-Yu Hsieh:
Test Response Compaction via Output Bit Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(10): 1534-1544 (2011) - 2010
- [j2]Kuen-Jong Lee, Tong-Yu Hsieh, Chin-Yao Chang, Yu-Ting Hong, Wen-Cheng Huang:
On-Chip SOC Test Platform Design Based on IEEE 1500 Standard. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1134-1139 (2010)
2000 – 2009
- 2009
- [c5]Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee:
Tolerance of performance degrading faults for effective yield improvement. ITC 2009: 1-10 - 2008
- [j1]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Trans. Reliab. 57(1): 204-214 (2008) - 2007
- [c4]Tong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You:
Test Efficiency Analysis and Improvement of SOC Test Platforms. ATS 2007: 463-466 - [c3]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE 2007: 1599-1604 - 2006
- [c2]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS 2006: 130-135 - 2005
- [c1]Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer:
A novel test methodology based on error-rate to support error-tolerance. ITC 2005: 9
Coauthor Index
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