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Jin-Mei Lai
Jinmei Lai
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
- [j25]YaoZhang Liu, Wei Xiong, Jian Wang, Jin-Mei Lai:
A new model for parametrically evaluating the routability of GRM FPGA. IEICE Electron. Express 21(3): 20230556 (2024) - [j24]Jiacheng Cao
, Wei Xiong, Jie Lu, Peilin Chen, Jian Wang, Jinmei Lai, Miaoqing Huang:
An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain-computer interfaces. Microelectron. J. 145: 106134 (2024) - [j23]Wei Xiong
A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1058-1071 (2024) - 2023
- [j22]Qingliang Liu
EdgeMedNet: Lightweight and Accurate U-Net for Implementing Efficient Medical Image Segmentation on Edge Devices. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4329-4333 (2023) - [c62]Jiacheng Cao, Ziyi Yang, Jie Lu, Jinmei Lai:
A High-Performance YOLOV5 Accelerator for Object Detection with Near Sensor Intelligence. ASICON 2023: 1-4 - [c61]Yanze Li, Zeyu Sun, Jianfan Zhang, Zhichao Wei, Jian Wang, Jinmei Lai:
An Accurate Area Model for FPGA Circuits at Advanced Technologies. ASICON 2023: 1-4 - [c60]Honghong Long, Yu Bai, Yanze Li, Jian Wang, Jinmei Lai:
Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm. ASICON 2023: 1-4 - 2022
- [j21]Yanze Li, Yufan Zhang, Jiafeng Liu, Jun Gong, Jian Wang, Jinmei Lai, Xinxuan Tao, Gang Qu:
AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design. Integr. 87: 231-240 (2022) - [j20]Huanlin Luo
3-D Auxiliary Classifier GAN for Hyperspectral Anomaly Detection via Weakly Supervised Learning. IEEE Geosci. Remote. Sens. Lett. 19: 1-5 (2022) - [j19]Qingliang Liu
An Efficient Channel-Aware Sparse Binarized Neural Networks Inference Accelerator. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1637-1641 (2022) - [c59]Wei Xiong
An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique. ACM Great Lakes Symposium on VLSI 2022: 275-280 - 2021
- [j18]Jiabao Gao, Yuchen Yao, Zhengjie Li, Jinmei Lai:
FCA-BNN: Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA. IEICE Trans. Inf. Syst. 104-D(8): 1367-1377 (2021) - [j17]Zhengjie Li, Jiabao Gao, Jinmei Lai:
HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure. IEICE Trans. Inf. Syst. 104-D(10): 1724-1733 (2021) - [c58]Yanze Li, Yufan Zhang, Jiafeng Liu, Jian Wang, Jinmei Lai, Gang Qu:
AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design. FCCM 2021: 256 - [c57]Qingliang Liu
TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference. ISCAS 2021: 1-5 - 2020
- [c56]Qingliang Liu
Stochastic Loss Function. AAAI 2020: 4884-4891 - [c55]Jiliang Zhang, Shuang Peng, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye, Xiangqi Wang:
HRAE: Hardware-assisted Randomization against Adversarial Example Attacks. ATS 2020: 1-6 - [c54]Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai:
INTB: A New FPGA Interconnect Model for Architecture Exploration. FPGA 2020: 325 - [c53]Yufan Zhang, Zhengjie Li, Jian Wang, Jinmei Lai:
FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA. FPGA 2020: 325 - [c52]Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai:
A Tile-based Interconnect Model for FPGA Architecture Exploration. ACM Great Lakes Symposium on VLSI 2020: 113-118 - [c51]Jia-Bao Gao, Jian Wang, Md Tanvir Arafin
FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs. SoCC 2020: 207-212
2010 – 2019
- 2019
- [c50]Timothy Dunlap, Gang Qu, Jinmei Lai:
A Polymorphic Circuit Interoperability Framework. ASICON 2019: 1-4 - [c49]Xinyu He, Xie Xie, Jinmei Lai, Jian Wang:
A Web-based Waveform Viewer for BR0101 Chip Testing Platform. ASICON 2019: 1-4 - [c48]Wei Liu, Weilin Cong, Chengyu Hu, Peng Lu, Jinmei Lai:
Balance of memory footprint and runtime for high-density routing in large-scale FPGAs. ASICON 2019: 1-4 - [c47]Jiafeng Liu, Zhiyin Lu, Xie Xie, Jian Wang, Jinmei Lai:
An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform. ASICON 2019: 1-4 - [c46]Zhi-Yin Lu, Jia-Feng Liu, Yunbing Pang, Zhengjie Li, Yufan Zhang, Jin-Mei Lai, Jian Wang:
A Low-delay Configurable Register for FPGA. ASICON 2019: 1-4 - [c45]Huanlin Luo, Yunbo Liu, Hai Ren, Tiantian Zhang, Jian Wang, Jinmei Lai:
An FPGA-based log-structure Flash memory system for space exploration. ASICON 2019: 1-4 - [c44]Yunbing Pang, Jiqing Xu
Research on Area Modeling Methodology for FPGA Interconnect Circuits. ASICON 2019: 1-4 - [c43]Xie Xie, Qinghua Duan, Jiafeng Liu, Jian Wang, Jinmei Lai:
Design and implementation of Serial ATA pbysical layer on FPGA. ASICON 2019: 1-4 - [c42]Jiqing Xu
Research on the impact of different benchmark circuits on the representative path in FPGAs. ASICON 2019: 1-3 - [c41]Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai:
Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. FPGA 2019: 121 - [c40]Zhengjie Li, Yuanlong Xiao
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. ACM Great Lakes Symposium on VLSI 2019: 93-98 - [c39]Chengyu Hu, Qinghua Duan, Liran Hu, Peng Lu, Zhengjie Li, Meng Yang, Jian Wang, Jinmei Lai:
An Analytical-based Hybrid Algorithm for FPGA Placement. ACM Great Lakes Symposium on VLSI 2019: 351-354 - 2018
- [j16]Hanyang Xu, Jian Wang, Jinmei Lai:
Design of a power efficient self-adaptive LVDS driver. IEICE Electron. Express 15(5): 20171276 (2018) - [j15]Chengyu Hu, Peng Lu, Meng Yang, Jian Wang, Jinmei Lai:
A SA-based parallel method for FPGA placement. IEICE Electron. Express 15(24): 20180943 (2018) - 2017
- [j14]Hua-Qing Wu, Mei-Ling Cheng
Flux balance analysis predicts Warburg-like effects of mouse hepatocyte deficient in miR-122a. PLoS Comput. Biol. 13(7) (2017) - [c38]Chuanliang Kang, Pei Yang, Jian Wang, Jinmei Lai:
A deep research on the chip verification platform based on network. ASICON 2017: 323-326 - [c37]Jiaqi Gu, Ruoyao Wang, Jian Wang, Jinmei Lai, Qinghua Duan:
Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration. ASICON 2017: 402-405 - [c36]Yuchen Yao, Zhiqian Zhang, Zhen Yang, Jian Wang, Jinmei Lai:
FPGA-based convolution neural network for traffic sign recognition. ASICON 2017: 891-894 - 2016
- [j13]Hanyang Xu, Jian Wang, Jinmei Lai:
Prototyping design of a flexible DSP block with pipeline structure for FPGA. IEICE Electron. Express 13(17): 20160676 (2016) - [j12]Yuanlong Xiao
A universal automatic on-chip measurement of FPGA's internal setup and hold times. IEICE Electron. Express 13(23): 20160810 (2016) - [c35]Zhen Yang, Jian Wang, Meng Yang, Jinmei Lai:
Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only). FPGA 2016: 280 - 2015
- [j11]Lei Li, Jinmei Lai:
Design and implementation of clock network for nanometer FPGA. IEICE Electron. Express 12(5): 20141180 (2015) - [j10]Zhen Yang, Chuanzeng Liang, Jian Wang, Jinmei Lai:
A new automatic method for testing interconnect resources in FPGAs based on general routing matrix. IEICE Electron. Express 12(20): 20150747 (2015) - [c34]Yuanpei Gao, Haijiang Ye, Jian Wang, Jinmei Lai:
FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique. ASICON 2015: 1-4 - [c33]Fang Sun, Jin-Mei Lai:
Iterative optimization algorithm for sound localization. ASICON 2015: 1-4 - [c32]Yuanlong Xiao, Jian Wang, Jinmei Lai:
A power efficient current-mode differential driver for FPGAs. ASICON 2015: 1-4 - 2014
- [j9]Meng Yang, Jinmei Lai, A. E. A. Almaini:
An Architecture Independent Packing Method for LUT-based Commercial FPGA. J. Comput. 9(5): 1131-1137 (2014) - [c31]Lei Li, Jian Wang, Jinmei Lai:
Novel FPGA clock network with low latency and skew (abstract only). FPGA 2014: 252 - 2013
- [j8]Meng Yang, Jiarong Tong, Jinmei Lai:
Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions. J. Comput. 8(10): 2520-2526 (2013) - [j7]Meng Yang, Jinmei Lai:
Optimisation of Mixed Polarity Reed-Muller Functions. J. Softw. 8(11): 2770-2774 (2013) - [c30]Jinmei Lai, Yanquan Luo, Qi Shao, Lichun Bao, Xueling Liu:
A high-resolution TDC implemented in a 90nm process FPGA. ASICON 2013: 1-3 - [c29]Huagang Li, Jian Wang, Jinmei Lai:
Weight-based FPGA placement algorithm with wire effect considered. ASICON 2013: 1-4 - [c28]Lei Li, Jian Wang, Jinmei Lai:
Improved unified interconnect unit for high speed and scalable FPGA. ASICON 2013: 1-4 - [c27]Hanyang Xu, Jinmei Lai:
A high throughput FPGA embedded DSP architecture design. ASICON 2013: 1-4 - [c26]Xinrui Zhang, Jian Wang, Dan Chen, Jinmei Lai, Lichun Bao, Xueling Liu:
The timing control design of 65nm block RAM in FPGA. ASICON 2013: 1-4 - [c25]Jinsong Mao, Hao Zhou, Haijiang Ye, Jinmei Lai:
FPGA bitstream compression and decompression using LZ and golomb coding (abstract only). FPGA 2013: 265 - [c24]Chun Zhu, Qiuli Li, Jian Wang, Jinmei Lai:
A novel multithread routing method for FPGAs (abstract only). FPGA 2013: 269 - [c23]Meng Yang, Jinmei Lai, Jiarong Tong:
Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD. FPL 2013: 1-4 - [c22]Chun Zhu, Jian Wang, Jinmei Lai:
A novel net-partition-based multithread FPGA routing method. FPL 2013: 1-4 - [c21]Jun Rong Wang, Dan Wang, Jin-Mei Lai:
A hierarchical parallel evolvable hardware based on network on chip. ReConFig 2013: 1-6 - 2012
- [j6]Liyun Wang, Chun Zhang, Liguang Chen, Jinmei Lai, Jiarong Tong:
A novel memristor-based rSRAM structure for multiple-bit upsets immunity. IEICE Electron. Express 9(9): 861-867 (2012) - [c20]M. Yang, Jinmei Lai, Hongying Xu:
Finite State Machine Synthesis Based on Relay-Based Algorithm. DSD 2012: 405-410 - [c19]Yong Fu, Chi Wang, Liguang Chen, Jinmei Lai:
A novel full coverage test method for CLBs in FPGA (abstract only). FPGA 2012: 267 - 2011
- [c18]Lei Li, Jian Wang, Yuan Wang, Jinmei Lai:
Research on design method of scalable Configurable IP Core. AHS 2011: 50-57 - [c17]Zhidong Mao, Liguang Chen, Yuan Wang, Jinmei Lai:
A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain. ASICON 2011: 67-70 - [c16]Xiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai:
FPGA interconnect timing library based on the statistical method. ASICON 2011: 393-396 - [c15]Xinrui Zhang, Liguang Chen, Liyun Wang, Jian Wang, Jinmei Lai:
The design and verification of SEU-hardened configurable DFF. ASICON 2011: 937-940 - [c14]Zhen Wang, Ding Xie, Jinmei Lai:
FPGA Interconnect Architecture Exploration Based on a Statistical Model. FPL 2011: 447-452
2000 – 2009
- 2009
- [j5]Sheng-An Lee, Chen-hsiung Chan, Tzu-Chi Chen, Chia-Ying Yang, Kuo-Chuan Huang, Chi-Hung Tsai, Jin-Mei Lai, Feng-Sheng Wang, Cheng-Yan Kao, Chi-Ying F. Huang:
POINeT: protein interactome with sub-network analysis and hub prioritization. BMC Bioinform. 10 (2009) - [j4]Shun-Fu Chen, Yue-Li Juang, Wei-Kang Chou, Jin-Mei Lai, Chi-Ying F. Huang
Inferring a transcriptional regulatory network of the cytokinesis-related genes by network component analysis. BMC Syst. Biol. 3: 110 (2009) - [c13]HuaQiu Yang, Liguang Chen, ShaoTeng Liu, HaiXiang Bu, Yuan Wang, Jinmei Lai:
A Flexible Bit-Stream Level Evolvable Hardware Platform Based on FPGA. AHS 2009: 51-56 - [c12]Fang Wu, Huowen Zhang, Lei Duan, Jinmei Lai, Yuan Wang, Jiarong Tong:
A delay-optimized universal FPGA routing architecture. ASP-DAC 2009: 135-136 - [c11]JIanDe Yu, Jinmei Lai:
A novel minloop SB design to improve FPGA routability. FPGA 2009: 286 - [c10]Xiaoxuan She, Jinmei Lai:
Self-adaptive evolution of complex logic circuits. WEAH 2009: 47-53 - 2008
- [j3]Sheng-An Lee, Chen-hsiung Chan, Chi-Hung Tsai, Jin-Mei Lai, Feng-Sheng Wang, Cheng-Yan Kao, Chi-Ying F. Huang
Ortholog-based protein-protein interaction prediction and its application to inter-species interactions. BMC Bioinform. 9(S-12) (2008) - [j2]Wei Cao, Hui Hou, Jiarong Tong, Jinmei Lai, Hao Min:
A high-performance reconfigurable VLSI architecture for vbsme in H.264. IEEE Trans. Consumer Electron. 54(3): 1338-1345 (2008) - [c9]Yabin Wang, Jing Xie, Jinmei Lai, Jiarong Tong:
Design and implementation of the configuration circuit for FDP FPGA. APCCAS 2008: 696-700 - [c8]Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min:
A novel dynamic reconfigurable VLSI architecture for H.264 transforms. APCCAS 2008: 1810-1813 - [c7]Chia-Ying Yang, Chao-Hui Chang, Ya-Ling Yu, Tsu-Chun Emma Lin, Sheng-An Lee, Chueh-Chuan Yen, Jinn-Moon Yang
PhosphoPOINT: a comprehensive human kinase interactome and phospho-protein database. ECCB 2008: 14-20 - [c6]Hui Hou, Wei Cao, Fan-jiong Zhang, Jinmei Lai, Jiarong Tong:
High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform. ICECS 2008: 486-489 - [c5]Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min:
A high-performance reconfigurable 2-D transform architecture for H.264. ICECS 2008: 606-609 - 2007
- [j1]Chun-Nan Hsu, Jin-Mei Lai, Chia-Hung Liu, Huei-Hun Tseng, Chih-Yun Lin, Kuan-Ting Lin
Detection of the inferred interaction network in hepatocellular carcinoma from EHCO (Encyclopedia of Hepatocellular Carcinoma genes Online). BMC Bioinform. 8 (2007) - 2005
- [c4]Chi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li:
A design of high speed double precision floating point adder using macro modules. ASP-DAC 2005: 11-12 - [c3]Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun:
Design of A 2.4-GHz integrated frequency synthesizer. ASP-DAC 2005: 21-22 - 2003
- [c2]Xinyu Wu, Zaiman Chen, Jinmei Lai, Qianling Zhang, Omar Wing, Junyan Ren:
Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation. ASP-DAC 2003: 885-890 - 2002
- [c1]Omar Wing, Tan Jun, Jinmei Lai, Junyan Ren, Qianling Zhang:
Iterative solution of ODE-PDE-AE systems for RF circuit simulation. ISCAS (4) 2002: 317-320
Coauthor Index
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last updated on 2024-10-16 20:30 CEST by the dblp team
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