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Wangqi Qiu
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2010 – 2019
- 2016
- [j3]Yuhan Zhou, Yong Zhang, Vivek Sarin, Wangqi Qiu, Weiping Shi:
Macro Model of Advanced Devices for Parasitic Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1721-1729 (2016)
2000 – 2009
- 2007
- [b1]Wangqi Qiu:
Fault simulation and test generation for small delay faults. Texas A&M University, College Station, USA, 2007 - 2006
- [c13]Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore:
Comparison of Delay Tests on Silicon. ITC 2006: 1-10 - 2005
- [j2]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
Longest-path selection for delay test under process variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1924-1929 (2005) - [c12]Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A vector-based approach for power supply noise analysis in test compaction. ITC 2005: 10 - [c11]Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker:
Static Compaction of Delay Tests Considering Power Supply Noise. VTS 2005: 235-240 - 2004
- [c10]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
Longest path selection for delay test under process variation. ASP-DAC 2004: 98-103 - [c9]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
PARADE: PARAmetric Delay Evaluation under Process Variation. ISQED 2004: 276-280 - [c8]Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran:
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. ITC 2004: 223-231 - [c7]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. MTV 2004: 97-102 - [c6]Wangqi Qiu, Weiping Shi:
Minimum moment Steiner trees. SODA 2004: 488-495 - [c5]Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi:
A Statistical Fault Coverage Metric for Realistic Path Delay Faults. VTS 2004: 37-42 - 2003
- [j1]Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A circuit level fault model for resistive bridges. ACM Trans. Design Autom. Electr. Syst. 8(4): 546-559 (2003) - [c4]Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi:
CodSim -- A Combined Delay Fault Simulator. DFT 2003: 79- - [c3]Wangqi Qiu, D. M. H. Walker:
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. ITC 2003: 592-601 - [c2]Wangqi Qiu, D. M. H. Walker:
Testing the Path Delay Faults of ISCAS85 Circuit c6288. MTV 2003: 19- - [c1]Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A Circuit Level Fault Model for Resistive Opens and Bridges. VTS 2003: 379-384
Coauthor Index
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