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Jae Young Hur
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2020 – today
- 2023
- [j12]Dai-Duong Tran
, Jae Young Hur
Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB Coalescing. IEEE Access 11: 91850-91860 (2023) - 2021
- [j11]Minshin Cho, Jae Young Hur, Wooyoung Jang:
Clean-prefetcher: look-ahead prefetching without cache pollution. IEICE Electron. Express 18(6): 20210027 (2021) - 2020
- [j10]Joonho Kong
Near-Threshold L1 Data Cache for Yield Management Under Process Variations. IEEE Access 8: 18558-18570 (2020) - [j9]Jae Young Hur
Page Table Compaction for TLB Coalescing. IEEE Access 8: 104814-104829 (2020) - [j8]Taejin Park, Jae Young Hur, Wooyoung Jang:
TLC STT-MRAM aware LLC for multicore processor. IEICE Electron. Express 17(24): 20200359 (2020) - [j7]Jae Young Hur:
Virtual Address Remapping with Configurable Tiles in Image Processing Applications. IEICE Trans. Inf. Syst. 103-D(2): 309-320 (2020)
2010 – 2019
- 2019
- [j6]Jae Young Hur
Adaptive Linear Address Map for Bank Interleaving in DRAMs. IEEE Access 7: 129604-129616 (2019) - [j5]Jae Young Hur:
Block Level TLB Coalescing for Buddy Memory Allocator. IEICE Trans. Inf. Syst. 102-D(10): 2043-2046 (2019) - [j4]Jae Young Hur
Contiguity Representation in Page Table for Memory Management Units. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 147-158 (2019) - 2017
- [c7]Jae Young Hur:
Representing Contiguity in Page Table for Memory Management Units. MCSoC 2017: 21-28 - 2012
- [j3]Jae Young Hur, Todor P. Stefanov
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays. IET Comput. Digit. Tech. 6(1): 59-68 (2012) - [j2]Jae Young Hur, Kees Goossens, Lotfi Mhamdi
Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays. IET Comput. Digit. Tech. 6(6): 396-405 (2012) - 2011
- [b1]Jae Young Hur:
Customizing and hardwiring on-chip interconnects in FPGAs. Delft University of Technology, Netherlands, 2011 - 2010
- [j1]Jae Young Hur, Stephan Wong, Todor P. Stefanov
Design Trade-offs in Customized On-chip Crossbar Schedulers. J. Signal Process. Syst. 58(1): 69-85 (2010) - [c6]Thomas Marconi, Jae Young Hur, Koen Bertels, Georgi Gaydadjiev
A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. SASP 2010: 87-92
2000 – 2009
- 2008
- [c5]Min Cheol Park, Moon Kyu Kwak, Hye Sung Cho, Kahp Y. Suh, Jae Young Hur, Sang-Hyun Park:
Yeast on a Chip - Single-cell Analyses of MAPK Signaling Pathways in Saccharomyces Cerevisiae using Cell Chips. BIODEVICES (2) 2008: 268-271 - [c4]Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah:
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. NOCS 2008: 45-54 - 2007
- [c3]Jae Young Hur, Stephan Wong, Stamatis Vassiliadis:
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs. ARC 2007: 49-60 - [c2]Jae Young Hur, Todor P. Stefanov
Systematic Customization of On-Chip Crossbar Interconnects. ARC 2007: 61-72 - [c1]Jae Young Hur, Todor P. Stefanov, Stephan Wong, Stamatis Vassiliadis:
Customizing Reconfigurable On-Chip Crossbar Scheduler. ASAP 2007: 210-215
Coauthor Index
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