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Paulo F. Flores
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2020 – today
- 2024
- [j22]Yuri Arbeletche, Guilherme Paim, Brunno Abreu, Sérgio Almeida, Eduardo Costa, Paulo F. Flores, Sergio Bampi:
MAxPy: A Framework for Bridging Approximate Computing Circuits to Its Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4748-4752 (2024) - 2023
- [j21]Brunno Alves de Abreu
, Albi Mema
Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 86-95 (2023) - [c47]Pedro Tauã Lopes Pereira, Guilherme Paim, Paulo F. Flores
AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation. DSN-W 2023: 183-186 - [c46]Fabio Pavanello, Cédric Marchand, Ian O'Connor, Régis Orobtchouk, Fabien Mandorlo, Xavier Letartre, Sébastien Cueff, Elena-Ioana Vatajelu, Giorgio Di Natale, Benoit Cluzel, Aurelien Coillet, Benoît Charbonnier, Pierre Noe, Frantisek Kavan, Martin Zoldak, Michal Szaj, Peter Bienstman, Thomas Van Vaerenbergh, Ulrich Rührmair, Paulo F. Flores
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. ETS 2023: 1-6 - [c45]Pedro Tauã Lopes Pereira, Guilherme Paim, Eduardo A. C. da Costa, Paulo F. Flores
Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design. NEWCAS 2023: 1-5 - [i1]Fabio Pavanello, Cédric Marchand, Ian O'Connor, Régis Orobtchouk, Fabien Mandorlo, Xavier Letartre, Sébastien Cueff, Elena-Ioana Vatajelu, Giorgio Di Natale, Benoit Cluzel, Aurelien Coillet, Benoît Charbonnier, Pierre Noe, Frantisek Kavan, Martin Zoldak, Michal Szaj, Peter Bienstman, Thomas Van Vaerenbergh, Ulrich Rührmair, Paulo F. Flores, Luís Guerra e Silva, Ricardo Chaves, Luís Miguel Silveira
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. CoRR abs/2305.03139 (2023) - 2020
- [j20]Ahmed Liacha
Radix-2 r recoding with common subexpression elimination for multiple constant multiplication. IET Circuits Devices Syst. 14(7): 990-994 (2020)
2010 – 2019
- 2017
- [c44]Ahmed Liacha
A variable RADIX-2r algorithm for single constant multiplication. NEWCAS 2017: 265-268 - 2016
- [j19]Levent Aksoy
A novel method for the approximation of multiplierless constant matrix vector multiplication. EURASIP J. Embed. Syst. 2016: 12 (2016) - 2015
- [j18]Levent Aksoy
Exact and Approximate Algorithms for the Filter Design Optimization Problem. IEEE Trans. Signal Process. 63(1): 142-154 (2015) - [j17]Diogo Brito
Quaternary Logic Lookup Table in Standard CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 306-316 (2015) - [j16]Nuno Neves
Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1287-1300 (2015) - [c43]Levent Aksoy
A Novel Method for the Approximation of Multiplierless Constant Matrix Vector Multiplication. EUC 2015: 98-105 - [c42]Levent Aksoy
Approximation of multiple constant multiplications using minimum look-up tables on FPGA. ISCAS 2015: 2884-2887 - 2014
- [j15]Levent Aksoy
A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures. Circuits Syst. Signal Process. 33(6): 1689-1719 (2014) - [j14]Levent Aksoy
Multiplierless Design of Folded DSP Blocks. ACM Trans. Design Autom. Electr. Syst. 20(1): 14:1-14:24 (2014) - [c41]Levent Aksoy, Paulo F. Flores
Optimization of design complexity in time-multiplexed constant multiplications. DATE 2014: 1-4 - [c40]Nuno Sebastião, Paulo F. Flores
Optimized ASIP architecture for compressed BWT-indexed search in bioinformatics applications. HPCS 2014: 527-534 - [c39]Levent Aksoy
Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA. ICCD 2014: 42-47 - [c38]Levent Aksoy
ECHO: A novel method for the multiplierless design of constant array vector multiplication. ISCAS 2014: 1456-1459 - 2013
- [j13]Nuno Sebastião
Configurable and scalable class of high performance hardware accelerators for simultaneous DNA sequence alignment. Concurr. Comput. Pract. Exp. 25(10): 1319-1339 (2013) - [j12]Levent Aksoy
Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 498-511 (2013) - [c37]Nuno Neves
BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment. ASAP 2013: 241-244 - [c36]Levent Aksoy, Eduardo Costa
Exploration of tradeoffs in the design of integer cosine transforms for image compression. ECCTD 2013: 1-4 - [c35]Ricardo Marques, Luis G. Silva, Paulo F. Flores, L. Miguel Silveira:
Improving SAT Solver Efficiency Using a Multi-Core Approach. FLAIRS 2013 - [c34]Levent Aksoy
SIREN: a depth-first search algorithm for the filter design optimization problem. ACM Great Lakes Symposium on VLSI 2013: 179-184 - [c33]Diogo Brito
Standard CMOS voltage-mode QLUT using a clock boosting technique. NEWCAS 2013: 1-4 - [c32]Levent Aksoy
Towards the least complex time-multiplexed constant multiplication. VLSI-SoC 2013: 328-331 - 2012
- [j11]Levent Aksoy
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. Integr. 45(3): 294-306 (2012) - [j10]Nuno Sebastião
Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase. Microprocess. Microsystems 36(2): 96-109 (2012) - [j9]Levent Aksoy
Optimization Algorithms for the Multiplierless Realization of Linear Transforms. ACM Trans. Design Autom. Electr. Syst. 17(1): 3:1-3:27 (2012) - [j8]Nuno Sebastião
Integrated Hardware Architecture for Efficient Computation of the $n$-Best Bio-Sequence Local Alignments in Embedded Platforms. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1262-1275 (2012) - [c31]Levent Aksoy, Eduardo Costa
Design of low-complexity digital finite impulse response filters on FPGAs. DATE 2012: 1197-1202 - [c30]Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Multiple tunable constant multiplications: Algorithms and applications. ICCAD 2012: 473-479 - [c29]Diogo Brito
Design and characterization of a QLUT in a standard CMOS process. ICECS 2012: 288-291 - 2011
- [j7]Cristiano Lazzari, Jorge R. Fernandes
Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. J. Low Power Electron. 7(2): 294-301 (2011) - [j6]Levent Aksoy
Finding the optimal tradeoff between area and delay in multiple constant multiplications. Microprocess. Microsystems 35(8): 729-741 (2011) - [c28]Levent Aksoy
Optimization of gate-level area in high throughput Multiple Constant Multiplications. ECCTD 2011: 588-591 - [c27]Levent Aksoy
Efficient shift-adds design of digit-serial multiple constant multiplications. ACM Great Lakes Symposium on VLSI 2011: 61-66 - [c26]Levent Aksoy
Design of low-power multiple constant multiplications using low-complexity minimum depth operations. ACM Great Lakes Symposium on VLSI 2011: 79-84 - [c25]Levent Aksoy
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. ISCAS 2011: 2737-2740 - [c24]Levent Aksoy
Multiplierless Design of Linear DSP Transforms. VLSI-SoC (Selected Papers) 2011: 73-93 - [c23]Levent Aksoy
A hybrid algorithm for the optimization of area and delay in linear DSP transforms. VLSI-SoC 2011: 148-153 - 2010
- [j5]Levent Aksoy
Search algorithms for the multiple constant multiplications problem: Exact and approximate. Microprocess. Microsystems 34(5): 151-162 (2010) - [c22]Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro:
A new quaternary FPGA based on a voltage-mode multi-valued circuit. DATE 2010: 1797-1802 - [c21]Levent Aksoy
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. DSD 2010: 3-10 - [c20]Nuno Sebastião
Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase. HPCS 2010: 16-23 - [c19]Cristiano Lazzari, Paulo F. Flores
Voltage-mode quaternary FPGAs: An evaluation of interconnections. ISCAS 2010: 869-872 - [c18]Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. PATMOS 2010: 84-93 - [c17]Diego Jaccottet, Eduardo Costa
Design of low-complexity and high-speed digital Finite Impulse Response filters. VLSI-SoC 2010: 292-297
2000 – 2009
- 2009
- [j4]Luís Gil, Paulo F. Flores, Luís Miguel Silveira:
PMSat: a parallel version of MiniSAT. J. Satisf. Boolean Model. Comput. 6(1-3): 71-98 (2009) - [j3]Pedro Marques Morgado, Paulo F. Flores
Generating realistic stimuli for accurate power grid analysis. ACM Trans. Design Autom. Electr. Syst. 14(3): 40:1-40:26 (2009) - 2008
- [j2]Levent Aksoy
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1013-1026 (2008) - [c16]Nuno Sebastião
Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units. DSD 2008: 181-188 - [c15]Pedro Marques Morgado, Paulo F. Flores
Generating Worst-Case Stimuli for Accurate Power Grid Analysis. PATMOS 2008: 247-257 - 2007
- [c14]Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Optimization of Area in Digital FIR Filters using Gate-Level Metrics. DAC 2007: 420-423 - [c13]Levent Aksoy
Minimum number of operations under a general number representation for digital filter synthesis. ECCTD 2007: 252-255 - [c12]Pedro Marques Morgado, Paulo F. Flores
Generating Realistic Stimuli for Accurate Power Grid Analysis. ISVLSI 2007: 233-238 - [c11]Levent Aksoy
Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. SiPS 2007: 424-429 - 2006
- [c10]Levent Aksoy
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. DAC 2006: 669-674 - [c9]Levent Aksoy
ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. ICECS 2006: 748-751 - [c8]Eduardo A. C. da Costa
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. SBCCI 2006: 161-166 - 2005
- [c7]Eduardo A. C. da Costa
Maximal sharing of partial terms in MCM under minimal signed digit representation. ECCTD 2005: 221-224 - [c6]Paulo F. Flores
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. ICCAD 2005: 13-16 - 2001
- [j1]Paulo F. Flores
An exact solution to the minimum size test pattern problem. ACM Trans. Design Autom. Electr. Syst. 6(4): 629-644 (2001)
1990 – 1999
- 1999
- [c5]Paulo F. Flores, Horácio C. Neto, João P. Marques Silva:
On Applying Set Covering Models to Test Set Compaction. Great Lakes Symposium on VLSI 1999: 8-11 - [c4]Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva:
Test pattern generation for width compression in BIST. ISCAS (1) 1999: 114-118 - [c3]Paulo F. Flores, José C. Costa, Horácio C. Neto, José Monteiro, João Marques-Silva:
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. VLSI Design 1999: 37-41 - 1998
- [c2]Paulo F. Flores, Horácio C. Neto, João P. Marques Silva:
An exact solution to the minimum size test pattern problem. ICCD 1998: 510-515 - 1997
- [c1]Vasco M. Manquinho, Paulo F. Flores, João P. Marques Silva, Arlindo L. Oliveira:
Prime Implicant Computation Using Satisfiability Algorithms. ICTAI 1997: 232-239
Coauthor Index
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