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VLSI Design, Volume 2012
Volume 2012, 2012
- S. Jayanthy
, M. C. Bhuvaneswari, Keesarapalli Sujitha:
Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm. 745861:1-745861:10 - Maxwell Walton, Omar Ahmed, Gary William Grewal, Shawki Areibi:
An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C. 793196:1-793196:11 - Roberta Piscitelli, Andy D. Pimentel
A Signature-Based Power Model for MPSoC on FPGA. 196984:1-196984:13 - Emanuele Cannella, Onur Derin, Paolo Meloni
Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks. 987209:1-987209:17 - Shiwani Singh, Tripti Sharma, K. G. Sharma
9T Full Adder Design in Subthreshold Region. 248347:1-248347:5 - Zhen-dong Zhang, Bin Wu, Yumei Zhou, Xin Zhang:
Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN. 948957:1-948957:7 - Yahya Jan, Lech Józwiak:
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors. 794753:1-794753:20 - Paolo Meloni
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper. 580584:1-580584:16 - Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari:
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design. 173079:1-173079:18 - Christina Gimmler-Dumont
A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection. 826350:1-826350:14 - Joyjit Mukhopadhyay, Soumya Pandit:
Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics. 505983:1-505983:13 - Muhammad Martuza
Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC. 242989:1-242989:10 - Guilherme Corrêa
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder. 748019:1-748019:20 - P. Balasubramanian, David A. Edwards, William B. Toms:
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders. 575389:1-575389:13 - Van Tam Nguyen, Frederic Villain, Yann Le Guillou:
Cognitive Radio RF: Overview and Challenges. 716476:1-716476:13 - Logan M. Rakai, Amin Farshidi, Laleh Behjat
A New Length-Based Algebraic Multigrid Clustering Algorithm. 395260:1-395260:14 - Khaled Grati
Power Consumption Models for Decimation FIR Filters in Multistandard Receivers. 870546:1-870546:15 - Massimo Bariani, Paolo Lambruschini, Marco Raggio
An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder. 413747:1-413747:14 - Philipp Schläfer, Christian Weis, Norbert Wehn
Design Space of Flexible Multigigabit LDPC Decoders. 942893:1-942893:10 - Maher Jridi
Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression. 209208:1-209208:12 - Christos Ttofis
Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms. 602737:1-602737:17 - Muhammad Awais
Flexible LDPC Decoder Architectures. 730835:1-730835:16 - Dionysios Diamantopoulos
A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems. 784945:1-784945:15 - Ashfaq Ahmed
Point DCT VLSI Architecture for Emerging HEVC Standard. 752024:1-752024:13 - Min Pan, Yue Xu, Yanheng Zhang, Chris Chu:
FastRoute: An Efficient and High-Quality Global Router. 608362:1-608362:18 - Sergio Saponara
Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing. 450302:1-450302:17 - Khaled Jerbi, Mickaël Raulet, Olivier Déforges, Mohamed Abid:
Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs. 298396:1-298396:14 - B. Bala Tripura Sundari
Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array. 268402:1-268402:15 - Guido Masera
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. 549768:1-549768:2 - Maurizio Martina, Muhammad Shafique
VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards. 102585:1-102585:3 - Maher Assaad
Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture. 546212:1-546212:7 - Leonardo Palacios-Luengas
Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map. 849120:1-849120:10 - Xin Zhao, Chris Chu:
Line Search-Based Inverse Lithography Technique for Mask Design. 589128:1-589128:9 - D. S. Harish Ram
A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths. 273276:1-273276:12 - Sheng-Chieh Huang, Hui-Min Wang, Wei-Yu Chen:
A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC. 809393:1-809393:13 - Chia-Hao Fang, I-tao Lung, Chih-Peng Fan
Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces. 657897:1-657897:6 - Lilia Zaourar, Yann Kieffer
A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions. 312808:1-312808:11
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