default search action
ACM Transactions on Architecture and Code Optimization (TACO), Volume 4
Volume 4, Number 1, March 2007
- Brad Calder, Dean M. Tullsen:
Introduction. 1 - Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky:
Architecting a reliable CMP switch architecture. 2 - Ruchira Sasanka, Man-Lap Li, Sarita V. Adve, Yen-Kuang Chen, Eric Debes:
ALP: Efficient support for all levels of parallelism for complex media applications. 3 - Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan:
Conserving network processor power consumption by exploiting traffic variability. 4 - Vassos Soteriou
, Noel Eisley, Li-Shiuan Peh:
Software-directed power-aware interconnection networks. 5 - Yuan-Shin Hwang, Jia-Jhe Li:
Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties. 6 - Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao:
Single-dimension software pipelining for multidimensional loops. 7
Volume 4, Number 2, June 2007
- Fred A. Bower, Daniel J. Sorin, Sule Ozev:
Online diagnosis of hard faults in microprocessors. 8 - Pierre Michaud
A study of thread migration in temperature-constrained multicores. 9 - Yu Chen, Fuxin Zhang:
Code reordering on limited branch offset. 10 - Andrei Sergeevich Terechko, Henk Corporaal:
Inter-cluster communication in VLIW architectures. 11 - Jialin Dou, Marcelo H. Cintra:
A compiler cost model for speculative parallelization. 12 - Wolfram Amme, Jeffery von Ronne
SSA-based mobile code: Implementation and empirical evaluation. 13
Volume 4, Number 3, September 2007
- Xiaodong Li, Ritu Gupta, Sarita V. Adve, Yuanyuan Zhou:
Cross-component energy management: Joint adaptation of processor and memory. 14 - Ron Gabor, Shlomo Weiss, Avi Mendelson:
Fairness enforcement in switch on event multithreading. 15 - Diego Andrade, Basilio B. Fraguela
Precise automatable analytical modeling of the cache behavior of codes with indirections. 16 - Kris Venstermans, Lieven Eeckhout, Koen De Bosschere:
Java object header elimination for reduced memory consumption in 64-bit virtual machines. 17 - Shu Xiao, Edmund Ming-Kit Lai:
VLIW instruction scheduling for minimal power variation. 18 - Sriraman Tallam, Rajiv Gupta
Unified control flow and data dependence traces. 19
Volume 4, Number 4, January 2008
- Engin Ipek, Sally A. McKee, Karan Singh, Rich Caruana, Bronis R. de Supinski, Martin Schulz
Efficient architectural design space exploration via predictive modeling. 1:1-1:34 - Yunhe Shi, Kevin Casey, M. Anton Ertl, David Gregg:
Virtual machine showdown: Stack versus registers. 2:1-2:36 - Jun Yan, Wei Zhang:
Exploiting virtual registers to reduce pressure on real registers. 3:1-3:18 - Zoe C. H. Yu, Francis C. M. Lau, Cho-Li Wang:
Object co-location and memory reuse for Java programs. 4:1-4:36 - Chuanjun Zhang:
Reducing cache misses through programmable decoders. 5:1-5:31 - Amit Golander, Shlomo Weiss:
Hiding the misprediction penalty of a resource-efficient high-performance processor. 6:1-6:32
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-18 20:34 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: