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Microprocessors and Microsystems, Volume 38
Volume 38, Number 1, February 2014
- Zbigniew Hajduk
:
An FPGA embedded microcontroller. 1-8 - Zai Jian Jia, Antonio Núñez
A two-phase design space exploration strategy for system-level real-time application mapping onto MPSoC. 9-21 - Ying Zhang, Lide Duan, Bin Li, Lu Peng, Xin Fu
Design configuration selection for hard-error reliable processors via statistical rules. 22-30 - Theodoros Lioris, Grigoris Dimitroulakos, Konstantinos Masselos:
An early memory hierarchy evaluation simulator for multimedia applications. 31-41 - Tareq Hasan Khan, Khan A. Wahid:
A portable wireless body sensor data logger and its application in video capsule endoscopy. 42-52 - Alexandre Yasuo Yamamoto, Cristinel Ababei:
Unified reliability estimation and management of NoC based chip multiprocessors. 53-63 - Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab
Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs. 64-75 - Ed Harcourt, James T. Perconti:
A SystemC library for specifying pipeline abstractions. 76-81 - Yongqing Wang, Fu-Chang Huang, Ye Tao, Ri-Bo Mu:
Relay-style Digital Speed Measurement Method and Dynamic Position Subdivision Method. 82-87 - Mohammad Hadi Mottaghi, Hamid R. Zarandi:
DFTS: A dynamic fault-tolerant scheduling for real-time tasks in multicore processors. 88-97 - Geng Tian, Michael Liebelt
An effectiveness-based adaptive cache replacement policy. 98-111
Volume 38, Number 2, March 2014
- Tiago Rogério Mück, Antônio Augusto Fröhlich
Aspect-oriented RTL HW design using SystemC. 113-123 - Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of the coarse-grained reconfigurable architecture DART with on-line error detection. 124-136 - Diego Andrade, Basilio B. Fraguela
Address independent estimation of the boundaries of cache performance. 137-151 - Yahya Jan, Lech Józwiak:
Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding. 152-169 - Faizal Arya Samman
Runtime connection-oriented guaranteed-bandwidth network-on-chip with extra multicast communication service. 170-181
Volume 38, Number 3, May 2014
- Jiajia Jiao, Yuzhuo Fu:
Exploiting and evaluating the potentials of the link addition method for NoC transient error mitigation. 183-196 - Chang-Jung Ku, Ching-Wen Chen, An Hsia, Chun-Lin Chen:
Linked instruction caches for enhancing power efficiency of embedded systems. 197-207 - Monika Kapus-Kolar:
On the global optimization of checking sequences for finite state machine implementations. 208-215 - Tan Yiyu, Yasushi Inoguchi, Yukinori Sato
Design and implementation of a two-dimensional sound field solver based on the Digital Huygens' Model. 216-225 - Lanfranco Lopriore:
Hardware support for memory protection in sensor nodes. 226-232 - Sungchan Kim, Soonhoi Ha:
System-level performance analysis of multiprocessor system-on-chips by combining analytical model and execution time variation. 233-245 - Arash Nejat, Seyed Mohammad Hossein Shekarian
A study on the efficiency of hardware Trojan detection based on path-delay fingerprinting. 246-252
Volume 38, Number 4, June 2014
- Diana Goehringer, Hamid Sarbazi-Azad, Rainer Stotzka:
Special Issue on Networks-on-Chip and Memories for Multicore Architectures. 253
- Ehsan Atoofian:
Boosting performance of transactional memory through O-GEHL predictors. 254-262 - Shirshendu Das, Hemangee K. Kapoor:
Victim retention for reducing cache misses in tiled chip multiprocessors. 263-275 - Mario Lodde, José Flich
Runtime home mapping for effective memory resource usage. 276-291
- Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, Kostas Siozios
A framework for rapid evaluation of heterogeneous 3-D NoC architectures. 292-303 - Chifeng Wang, Nader Bagherzadeh
Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip. 304-315 - Tianzhou Chen, Weiwei Fu, Bin Xie, Chao Wang:
Packet triggered prediction based task migration for network-on-chip. 316-324 - Coskun Çelik, Cüneyt F. Bazlamaçci
Evaluation of energy and buffer aware application mapping for networks-on-chip. 325-336 - Ludovic Devaux, Sébastien Pillement
OCEAN, a flexible adaptive Network-On-Chip for dynamic applications. 337-357
Volume 38, Number 5, July 2014
- Gábor Gyepes, Viera Stopjaková
A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays. 359-367 - Nan Li, Elena Dubrova:
Area-efficient high-coverage LBIST. 368-374 - Sani Abba, Jeong-A Lee:
A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip. 375-398 - Behnam Khodabandeloo, Ahmad Khonsari
Scenario-based quasi-static task mapping and scheduling for temperature-efficient MPSoC design under process variation. 399-414 - Yuang Zhang
A survey of memory architecture for 3D chip multi-processors. 415-430 - Yu-Kuen Lai, Chun-Chieh Lee, Bo-Hsun Huang, Theophilus Wellem
Real-time detection of changes in network with OpenFlow based on NetFPGA implementation. 431-442 - Antônio de Pádua Finazzi, Gustavo Brito de Lima, Luiz Carlos Gomes de Freitas, Ernane Antônio Alves Coelho, Valdeir José Farias, Luiz C. G. Freitas:
Proposal for preprogrammed control applied to a current-sensorless PFC boost converter. 443-450 - Chen Zhao, Kuizhi Mei, Nanning Zheng:
Design of write merging and read prefetching buffer in DRAM controller for embedded processor. 451-457 - Zhilei Chai, Xinglong Shao, Yuanpu Zhang, Wenmin Yang, Qin Wu:
Accelerating image boundary detection by hardware parallelism. 458-469 - Valery Sklyarov
High-performance implementation of regular and easily scalable sorting networks on an FPGA. 470-484 - Po-Yueh Chen, Chiung-Hsien Jen:
Register swapping schemes for low power execution. 485-495 - T. Ananthan, M. V. Vaidyan:
An FPGA-based parallel architecture for on-line parameter estimation using the RLS identification algorithm. 496-508 - Antonio Carlos Schneider Beck, Mateus Beck Rutzig
A transparent and adaptive reconfigurable system. 509-524
Volume 38, Number 6, August 2014
- Masoud Daneshtalab
Special issue on many-core embedded systems. 525 - Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Authenticated encryption on FPGAs from the static part to the reconfigurable part. 526-538 - Jia Huang, Simon Barner, Andreas Raabe, Christian Buckl, Alois C. Knoll
A framework for reliability-aware embedded system design on multiprocessor platforms. 539-551 - Mohammad Maghsoudloo
Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies. 552-564
- Lorena Anghel
Editorial. 565-566 - Antonio Miele
A fault-injection methodology for the system-level dependability analysis of multiprocessor embedded systems. 567-580 - Pedro Reviriego, Serdar Zafer Can, Çagri Eryilmaz, Juan Antonio Maestro
Exploiting processor features to implement error detection in reduced precision matrix multiplications. 581-584 - Stelios Neophytou
Multiple detection test generation with diversified fault partitioning paths. 585-597 - Serdar Zafer Can, Gulay Yalcin, Oguz Ergin
Bit Impact Factor: Towards making fair vulnerability comparison. 598-604 - Petr Pfeifer
A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices. 605-619 - Michael G. Dimopoulos, Yi Gang, Lorena Anghel
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. 620-635
Volume 38, Number 7, October 2014
- Madhushika M. E. Karunarathna, Yu-Chu Tian
Domain-specific application analysis for customized instruction identification. 637-648 - Asim Datta
A dsPIC based novel digital sinusoidal pulse-width modulation technique for voltage source inverter applications. 649-658 - Layla Horrigue, Taoufik Saidani
An efficient hardware implementation of MQ decoder of the JPEG2000. 659-668 - Yuhai Li, Kuizhi Mei, Yuehu Liu, Nanning Zheng, Yi Xu:
LDBR: Low-deflection bufferless router for cost-sensitive network-on-chip design. 669-680 - Amir Yazdanbakhsh
Implementation-aware selection of the custom instruction set for extensible processors. 681-691 - Erulappan Sakthivel, Veluchamy Malathi, Muruganantham Arunraja:
MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture. 692-706 - Syed Zohaib Gilani, Taejoon Park, Nam Sung Kim:
Low-cost scratchpad memory organizations using heterogeneous cell sizes for low-voltage operations. 707-716 - Xingxing Jin, Brian Daku, Seok-Bum Ko
Improved GPU SIMD control flow efficiency via hybrid warp size mechanism. 717-729 - Javier Echanobe
An FPGA-based multiprocessor-architecture for intelligent environments. 730-740
Volume 38, Number 8, Part A, November 2014
- José Silva Matos, Francesco Leporati:
MICPRO DSD 2013 Special Issue. 741-742 - Vincent Berg
A flexible radio transceiver for TVWS based on FBMC. 743-753 - Jirí Balcárek, Petr Fiser, Jan Schmidt:
On don't cares in test compression. 754-765 - Yarkin Doröz, Erdinç Öztürk, Berk Sunar:
A million-bit multiplier architecture for fully homomorphic encryption. 766-775 - Daniele Bortolotti
An ultra-low power resilient multi-core architecture with static and dynamic tolerance to ambient temperature-induced variability. 776-787 - Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Kolin Paul:
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. 788-802 - Mehmet Ali Arslan, Krzysztof Kuchcinski
Instruction selection and scheduling for DSP kernels. 803-813 - Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny:
Designing single-cycle long links in hierarchical NoCs. 814-825 - Guangda Zhang, Wei Song, Jim D. Garside
Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. 826-842
Volume 38, Number 8, Part B, November 2014
- Peter M. Athanas, René Cumplido, Claudia Feregrino Uribe, Eduardo de la Torre:
Introduction to Special issue on FPGA Devices and Applications. 843-844 - Daniel Kliem, Sven-Ole Voigt:
Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning. 845-859 - Robin Bonamy, Sébastien Bilavarn, Daniel Chillet
Power consumption models for the use of dynamic and partial reconfiguration. 860-872 - Shweta Jain-Mendon, Ron Sass:
A hardware-software co-design approach for implementing sparse matrix vector multiplication on FPGAs. 873-888 - Tannous Frangieh, Peter M. Athanas:
A design assembly framework for FPGA back-end acceleration. 889-898 - Wei He, Andrés Otero
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. 899-910 - Andreas Agne, Hendrik Hangmann, Markus Happe
Seven recipes for setting your FPGA on fire - A cookbook on heat generators. 911-919
- Francesco Leporati, Lech Józwiak:
Preface. 920 - Salvador Trujillo, Alfons Crespo
MultiPARTES: Multi-core partitioning and virtualization for easing the certification of mixed-criticality systems. 921-932 - Ivan Kastelan
E2LP: A unified embedded engineering learning platform. 933-946 - Erkan Diken, Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal, Felipe Augusto Chies:
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. 947-959 - Héctor Posadas, Alejandro Nicolás, Pablo Peñil
Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project. 960-975 - Roberto Giorgi, Rosa M. Badia
TERAFLUX: Harnessing dataflow in next generation teradevices. 976-990
- Hoda Naghibi Jouybari
A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips. 991-999 - Mostafa Elhoushi
Model of a hybrid processor executing C++ with additional quantum functions. 1000-1011 - Chenglong Xiao, Emmanuel Casseau, Shanshan Wang, Wanjun Liu:
Automatic custom instruction identification for application-specific instruction set processors. 1012-1024 - Fenglong Song, Shibin Tang, Wenming Li, Futao Miao, Hao Zhang, Dongrui Fan
CRANarch: A feasible processor micro-architecture for Cloud Radio Access Network. 1025-1036 - Eman Kamel Gawish, M. Watheq El-Kharashi, Mohamed Fathy Abu-ElYazeed:
Variability-tolerant routing algorithms for Networks-on-Chip. 1037-1045 - Moein Kianpour
A conventional design and simulation for CLB implementation of an FPGA quantum-dot cellular automata. 1046-1062 - Vikas Kumar
CORDIC-based VLSI architecture for real time implementation of flat top window. 1063-1071 - Mojtaba Valinataj
A novel self-checking carry lookahead adder with multiple error detection/correction. 1072-1081
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