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20th RSP 2009: Paris, France
- Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, Shortening the Path from Specification to Prototype, RSP 2009, Paris, France, 23-26 June 2009. IEEE Computer Society 2009, ISBN 978-0-7695-3690-3
Formal Methods, Synthesis & Quality Assurance
- Joseph Porter, Péter Völgyesi, Nicholas Kottenstette, Harmon Nine, Gabor Karsai
, Janos Sztipanovits:
An Experimental Model-Based Rapid Prototyping Environment for High-Confidence Embedded Software. 3-10 - André Sülflow, Ulrich Kühne, Görschwin Fey
WoLFram- A Word Level Framework for Formal Verification. 11-17 - Nasreddine Aoumeur, Kamel Barkaoui, Gunter Saake:
Rapid-Prototyping of Adaptive Component-Based Systems Using Runtime Aspectual Interactions. 18-25 - Xavier Renault, Fabrice Kordon, Jérôme Hugues:
Adapting Models to Model Checkers, A Case Study : Analysing AADL Using Time or Colored Petri Nets. 26-33 - Christos Pavlatos
A Formal Method for Rapid SoC Prototyping. 34-37
Communication Aspects
- Bhasker Jakka, Dillip Dash, Caner Yalcin, Ly Dang, Omar Mire, Aldo Cometti:
A Flexible High Throughput FPGA Based Prototype Platform for RW Channel Development. 41-47 - Alexandre Chagoya-Garzon, Xavier Guerin, Frédéric Rousseau, Frédéric Pétrot, Davide Rossetti, Alessandro Lonardo, Piero Vicini
Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips. 48-54 - Amit Kumar Singh, Wu Jigang, Alok Prakash, Thambipillai Srikanthan:
Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms. 55-60 - Sven Schneider, André Meisel, Wolfram Hardt:
Communication-Aware Hierarchical Online-Placement in Heterogeneous Reconfigurable Systems. 61-67 - Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser:
Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic Generation. 68-71
Prototyping Methodology
- Tiago de Albuquerque Reis, Antônio Augusto Fröhlich
Operating System Support for Difference-Based Partial Hardware Reconfiguration. 75-80 - Joseph C. Libby, Kenneth B. Kent
A Methodology for Rapid Optimization of HandelC Specifications. 81-87 - Chafic Jaber, Andreas Kanstein
High-Level System Modeling for Rapid HW/SW Architecture Exploration. 88-94 - John Cole, Larry Garey, Kenneth B. Kent
Rapid Prototyping Projection Algorithms with FPGA Technology. 95-101 - Laura Carnevali, Dario D'Amico, Lorenzo Ridi, Enrico Vicario
Automatic Code Generation from Real-Time Systems Specifications. 102-105
Hardware Modeling
- Ulrich Kühne, Sven Beyer, Christian Pichler:
Generating an Efficient Instruction Set Simulator from a Complete Property Suite. 109-115 - Nicolas Pouillon, Alexandre Bécoulet
A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs. 116-122 - Benjamin Glas, Alexander Klimm, Klaus D. Müller-Glaser, Jürgen Becker:
Configuration Measurement for FPGA-based Trusted Platforms. 123-129 - Atif Raza Jafri
Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer. 130-133
Performance Optimization
- Dongwon Lee, Shuvra S. Bhattacharyya
High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems. 137-144 - Lieu My Chuong, Siew Kei Lam
Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA. 145-151 - Santanu Kumar Dash
Instruction Cache Tuning for Embedded Multitasking Applications. 152-158 - Zahir Larabi, Yves Mathieu, Stéphane Mancini:
Efficient Data Access Management for FPGA-Based Image Processing SoCs. 159-165 - Michalis Platsis, Ioannis Papaefstathiou, Dimitrios Meintanis:
Design and Implementation of an UWB Digital Transmitter Based on the Multiband OFDM Physical Layer Proposal. 166-169
Automotive & Industrial Applications
- Matthias Heinz, Verena Hoss, Klaus D. Müller-Glaser:
Physical Layer Extraction of FlexRay Configuration Parameters. 173-180 - Kevin Andryc, Russell Tessier, Patrick Kelly:
An Interactive Approach to Timing Accurate PCI-X Simulation. 181-187 - Martin Hillenbrand, Klaus D. Müller-Glaser:
An Approach to Supply Simulations of the Functional Environment of ECUs for Hardware-in-the-Loop Test Systems Based on EE-architectures Conform to AUTOSAR. 188-195 - Jean Saad, Amer Baghdadi
FPGA-based Radar Signal Processing for Automotive Driver Assistance System. 196-199
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