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ReConFig 2014: Cancun, Mexico
- 2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig14, Cancun, Mexico, December 8-10, 2014. IEEE 2014, ISBN 978-1-4799-5944-0
- Edward A. Lee:
Keynote - It's about time. 1 - Thomas P. Flatley:
Keynote - SpaceCube - A family of reconfigurable hybrid on-board science data processors. 1-2 - Jan Gray:
Keynote - The past and future of FPGA soft processors. 1 - Johanna Sepúlveda, Guy Gogniat
, Daniel Florez, Jean-Philippe Diguet, César Pedraza, Marius Strum:
3D-LeukoNoC: A dynamic NoC protection. 1-6 - Shijie Zhou, Sihan Zhao, Viktor K. Prasanna:
400 Gbps energy-efficient multi-field packet classification on FPGA. 1-6 - Timm Bostelmann, Sergei Sawitzki:
A conceptual toolchain for an application domain specific reconfigurable logic architecture. 1-4 - Shinya Takamaeda-Yamazaki, Kenji Kise:
A framework for efficient rapid prototyping by virtually enlarging FPGA resources. 1-8 - Maik Ender
A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems. 1-6 - James Demma, Peter Athanas:
A hardware generator for factor graph applications. 1-8 - Jones Yudi Mori
A high-level analysis of a multi-core vision processor using SystemC and TLM2.0. 1-6 - C. Wilson, Paolo Zicari, Stefan Craciun, P. Gauvin, E. Carlisle, Alan D. George
A power-efficient real-time architecture for SURF feature extraction. 1-8 - Bernhard Jungk, Leandro Rodrigues Lima, Matthias Hiller
A systematic study of lightweight hash functions on FPGAs. 1-6 - Poona Bahrebar, Dirk Stroobandt:
Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip. 1-8 - Di Wu, Andreas Moshovos:
Advanced branch predictors for soft processors. 1-6 - Osvaldo Navarro, Michael Hübner:
An adaptive victim cache scheme. 1-4 - Jotham Vaddaboina Manoranjan, Kenneth S. Stevens:
An a-FPGA architecture for relative timing based asynchronous designs. 1-6 - Benedikt Janßen, Michael Hübner, Timo Jaeschke
An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 SuperSpeed. 1-4 - Alfredo Espinoza-Rhoton, Luis F. Gonzalez-Perez, J. L. Ponce, Borrayo-S. Hector, Lennin C. Yllescas-Calderon, Ramón Parra-Michel, Hassan Aboushady:
An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm. 1-6 - Daniel Kirschberger, Holger Flatt, Jürgen Jasperneite
An architectural approach for reconfigurable industrial I/O devices. 1-6 - Saki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu:
Area-efficient dynamically reconfigurable protocol-processing-hardware for access network communications SoC. 1-6 - Gang Chen, Biao Hu, Kai Huang, Alois C. Knoll
Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs. 1-8 - Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai:
An AWF digital spectrometer for a radio telescope. 1-6 - Ekawat Homsirikamol, Kris Gaj:
Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study. 1-8 - Shanyuan Gao, Jeremy Chritz:
Characterization of OpenCL on a scalable FPGA architecture. 1-6 - Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado:
Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead. 1-6 - Tom Davidson, Dirk Stroobandt:
Data path analysis for dynamic circuit specialisation. 1-8 - Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri:
Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA. 1-6 - Gavin Vaz, Heinrich Riebler
Deferring accelerator offloading decisions to application runtime. 1-8 - Fynn Schwiegelshohn, Michael Hübner:
Design of an attention detection system on the Zynq-7000 SoC. 1-6 - Markus Happe
Dynamic protocol stacks in smart camera networks. 1-6 - Quang-Hai Khuat, Daniel Chillet
Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC. 1-4 - Felipe A. P. de Figueiredo
Efficient FPGA-based implementation of a CAZAC sequence generator for 3GPP LTE. 1-6 - Tobias Wiersema
Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA. 1-6 - Sam Skalicky, Tyler Kwolek, Sonia López, Marcin Lukowiak:
Enabling FPGA support in Matlab based heterogeneous systems. 1-6 - Viet Vu Duy, Oliver Sander, Timo Sandmann, Steffen Bähr, Jan Heidelberger, Jürgen Becker
Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization. 1-6 - Andrea Sanny, Yi-Hua E. Yang, Viktor K. Prasanna:
Energy-efficient histogram on FPGA. 1-6 - Konrad Häublein, Marc Reichenbach
Fast and generic hardware architecture for stereo block matching applications on embedded systems. 1-6 - Alexander Fell
Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures. 1-8 - Mohammad A. Zare, Rajesh G. Kavasseri
FPGA-based design and implementation of direct torque control for induction machines. 1-6 - Misael Lopez-Ramirez
FPGA-based reconfigurable unit for real-time power quality index estimation. 1-6 - David Uliana, Peter M. Athanas, Krzysztof Kepa
FPGA-based accelerator development for non-engineers. 1-6 - Daniel Tortei Tertei, Jonathan Piat, Michel Devy:
FPGA design and implementation of a matrix multiplier based accelerator for 3D EKF SLAM. 1-6 - Marco Tulio Ramírez-Torres, José S. Murguía Ibarra
FPGA implementation of a reconfigurable image encryption system. 1-4 - Jorge Echavarria
FSM merging and reduction for IP cores watermarking using Genetic Algorithms. 1-7 - Vladimir Rodriguez
A hardware architecture for filtering irreducible testors. 1-4 - Pavel G. Zaykov, Georgi Kuzmanov, Anca Mariana Molnos, Kees Goossens:
Hardware Task-Status Manager for an RTOS with FIFO communication. 1-8 - Andreas Emeretlis, George Theodoridis, George-Othon Glentis
High-performance FPGA implementations of volterra DFEs for optical fiber systems. 1-8 - Friedrich Wiemer
High-speed implementation of bcrypt password search using special-purpose hardware. 1-6 - Vaibhav R. Gandhi, Yun Rock Qu, Viktor K. Prasanna:
High-throughput hash-based online traffic classification engines on FPGA. 1-6 - Tomas Drahonovsky, Martin Rozkovec
A highly flexible reconfigurable system on a Xilinx FPGA. 1-6 - Peter Reichel, Jens Döge
Hardware/software infrastructure for ASIC commissioning and rapid system prototyping. 1-6 - Rico Backasch, Gerald Hempel, Stefan Werner, Sven Groppe
Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation. 1-6 - Amit Kulkarni, Tom Davidson, Karel Heyse, Dirk Stroobandt:
Improving reconfiguration speed for dynamic circuit specialization using placement constraints. 1-6 - Tobias Kenter, Henning Schmitz, Christian Plessl
Kernel-centric acceleration of high accuracy stereo-matching. 1-8 - Zhuo Qian, Martin Margala
Low power RAM-based hierarchical CAM on FPGA. 1-4 - Lei Xu
LUT based secure cloud computing - An implementation using FPGAs. 1-6 - Chuan Cheng, Christos-Savvas Bouganis
Memory optimisation for hardware induction of axis-parallel decision tree. 1-5 - Sam Skalicky, Sonia López, Marcin Lukowiak, Christopher A. Wood:
Mission control: A performance metric and analysis of control logic for pipelined architectures on FPGAs. 1-6 - Cristinel Ababei, Rajesh G. Kavasseri
Net reordering and multicommodity flow based global routing for FPGAs. 1-6 - Byron Navas, Johnny Öberg, Ingo Sander
On providing scalable self-healing adaptive fault-tolerance to RTR SoCs. 1-6 - Vignesh Adhinarayanan
On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization. 1-7 - Khaled E. Ahmed, Mohammed M. Farag
Overloaded CDMA bus topology for MPSoC interconnect. 1-7 - Tassadaq Hussain, Nehir Sönmez
PAMS: Pattern Aware Memory System for embedded systems. 1-7 - Alexandra Kourfali
Parameterised FPGA reconfigurations for efficient test set generation. 1-6 - Ryo Konomura, Koichi Hori:
Phenox: Zynq 7000 based quadcopter robot. 1-6 - Karim M. A. Ali, Rabie Ben Atitallah, Saïd Hanafi, Jean-Luc Dekeyser:
A generic pixel distribution architecture for parallel video processing. 1-8 - Thomas B. Preußer, Oliver Knodel
PoC-align: An open-source alignment accelerator using FPGAs. 1-6 - Pei Luo
Power analysis attack on hardware implementation of MAC-Keccak on FPGAs. 1-7 - Enrique Mariano Lizarraga
A practical scheme for implementing dynamic spectral precoding in OFDM. 1-6 - Ali Asgar Sohanghpurwala, Peter M. Athanas, Andrew Love:
A device-agnostic tool for precomputing legal placements in modular design flows. 1-5 - Jens Rettkowski, Diana Göhringer:
RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systems. 1-6 - Quang-Hoa Le, Emmanuel Casseau, Antoine Courtay:
Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture. 1-6 - Simon Schulz, Oliver Bringmann, Thomas Schweizer, Wolfgang Rosenstiel:
Rotated parallel mapping: A novel approach for mapping data parallel applications on CGRAs. 1-6 - Pei Luo
Side-channel power analysis of different protection schemes against fault attacks on AES. 1-6 - Naoyuki Fujita, Toshifumi Yanagisawa, Hirohisa Kurosaki, Hiroshi Oda:
The speed-up of detection of space debris using "InterP" and "FLOPS2D". 1-6 - Benoit Chappet de Vangel, César Torres-Huitzil, Bernard Girau:
Spiking dynamic neural fields architectures on FPGA. 1-6 - Yu Bai, Mingjie Lin:
Stochastically computing discrete Fourier transform with reconfigurable digital fabric. 1-7 - An Hung Nguyen
The FPGA implementation of an image registration algorithm using binary images. 1-4 - Brad White, Brent E. Nelson:
Tincr - A custom CAD tool framework for Vivado. 1-6 - Jose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil:
TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces. 1-6 - Mohammed M. Farag
Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores. 1-6 - Hongyuan Ding, Miaoqing Huang:
A unified OpenCL-flavor programming model with scalable hybrid hardware platform on FPGAs. 1-7 - Carlos Andres Lara-Nino
Versatile educational and research robotic platform based on reconfigurable hardware. 1-6 - Kaveh Aasaraai, Andreas Moshovos:
What limits the operating frequency of a soft processor design. 1-6 - Rui Policarpo Duarte, Christos-Savvas Bouganis
Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs. 1-7
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