default search action
35th SoCC 2022: Belfast, UK
- Sakir Sezer, Thomas Büchner, Jürgen Becker, Andrew Marshall, Fahad Siddiqui, Tanja Harbaum, Kieran McLaughlin:
35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, United Kingdom, September 5-8, 2022. IEEE 2022, ISBN 978-1-6654-5985-3 - Sandeep Sunkavilli, Nishanth Goud Chennagouni, Qiaoyan Yu:
DPReDO: Dynamic Partial Reconfiguration enabled Design Obfuscation for FPGA Security. 1-6 - Amit Kumar Kabat, Shubhang Pandey, Venkatesh Tiruchirai Gopalakrishnan:
Performance evaluation of High Bandwidth Memory for HPC Workloads. 1-6 - Taha Soliman, Amro Eldebiky, Cecilia De la Parra, Andre Guntoro, Norbert Wehn:
Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators. 1-6 - Anagha Nimbekar, Chandrasekhara Srinivas Vatti, Y. V. Sai Dinesh
, Sunidhi Singh, Tarun Gupta, Ramesh Reddy Chandrapu, Amit Acharyya:
Low Complexity Reconfigurable-Scalable Architecture Design Methodology for Deep Neural Network Inference Accelerator. 1-6 - Olivia Chen
Design and Implementation of Stochastic Neural Networks Using Superconductor Quantum-Flux-Parametron Devices. 1-6 - Chuanchao Lu, Yijun Cui, Ayesha Khalid, Chongyan Gu, Chenghua Wang, Weiqiang Liu:
A Novel Combined Correlation Power Analysis (CPA) Attack on Schoolbook Polynomial Multiplication in Lattice-based Cryptosystems. 1-6 - Luka Daoud, Nader Rafla:
Energy-Efficient Black Hole Router Detection in Network-on-Chip. 1-6 - Lukas Jünger, Antonios Salios, Peter Blöcher, Rainer Leupers:
Virtual Platform Acceleration through Userspace Host Execution. 1-6 - Jaya Dofe:
Thermal Side-channel Leakage Protection in Monolithic Three Dimensional Integrated Circuits. 1-2 - Uchechukwu Leo Udeji, Martin Margala:
FPGA Implementation of Addition-based CORDIC-SNN With Izhikevich Neurons. 1-6 - Matthieu Parizy, Przemyslaw Sadowski, Nozomu Togawa:
Cardinality Constrained Portfolio Optimization on an Ising Machine. 1-6 - Hiroki Nishimoto, Renyuan Zhang, Yasuhiko Nakashima:
Application and Evaluation of Quantization for Narrow Bit-width Resampling of Sequential Monte Carlo. 1-6 - Mohamed Watfa, Alberto García Ortiz, Gilles Sassatelli:
Energy-Based Analog Neural Network Framework. 1-6 - Xingye Liu, Paul Ampadu:
A Scalable DC/DC Converter with Fast Load Transient Response and Security Improvement. 1-6 - Omar A. Yeste Ojeda
The Case for SoC in Future Radio Astronomy. 1-2 - Agshare Dheeraj, Pabitra Das
Modeling Attacks Resilient Multiple PUF-CPRNG Architecture Design Methodology. 1-6 - Florian Schade, Tobias Dörr
Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based Development. 1-2 - Haohui Jia, Na Chen, Renyuan Zhang, Minoru Okada:
Non-deterministic Quantization for mmWave Beam Prediction. 1-6 - Abdelrahman G. Habib, Mohamed Dessouky:
A General Algorithm for Loop-gain and TDC-resolution Optimization in an ADPLL with a 2-bit TDC Phase detector. 1-6 - Xiangye Wei
A New Perspective of Inscribing Temporal Encryption on Spatial MPV Imprints for PUF Design. 1-6 - Hongsup Shin:
Data-Centric Machine Learning Pipeline for Hardware Verification. 1-2 - Andrea Bartolini, Federico Ficarelli
Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers. 1-6 - Jinteng Jiao, He Li, Yanzhao Feng, Chengdong Qian, Qiang Liu:
In-depth Analysis of the Effects of Electromagnetic Fault Injection Attack on a 32-bit MCU. 1-6 - Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin:
An Efficient FPGA Accelerator for Point Cloud. 1-6 - Xiangdong Wei, Mohamed El-Hadedy
RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoT. 1-6 - Ahmad Al-Zoubi, Gianluca Martino
CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL. 1-6 - Saeid Gorgin, MohammadHosein Gholamrezaei, Danial Javaheri
kNN-MSDF: A Hardware Accelerator for k-Nearest Neighbors Using Most Significant Digit First Computation. 1-6 - Erjola Lalo, Andreas Sailer, Jürgen Mottok, Christian Siemers:
Overhead-Aware Schedule Synthesis for Logical Execution Time (LET) in Automotive Systems. 1-6 - Peiyao Sun, Basel Halak
Towards Hardware Trojan Resilient Design of Convolutional Neural Networks. 1-6 - Binayak Tiwari, Mei Yang, Xiaohang Wang, Yingtao Jiang:
In-Network Accumulation: Extending the Role of NoC for DNN Acceleration. 1-6 - Thomas Garbay, Khalil Hachicha, Petr Dobiás, Wilfried Dron, Pedro Lusich, Imane Khalis, Andrea Pinna, Bertrand Granado:
Accurate Estimation of the CNN Inference Cost for TinyML Devices. 1-6 - Sai Praveen Kadiyala, Xiaolan Li, Wonjun Lee, Andrew Catlin:
Securing Microservices Against Password Guess Attacks using Hardware Performance Counters. 1-6 - Fabian Kempf, Julian Höfer
Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors. 1-6 - Sharath Patil, Bhanu Singh, Raunak Borwankar, Martin Margala:
Novel Pulse Detection System Using Differentiation: Optical Experimental Results. 1-5 - Wenye Liu, Weiyang He, Bowen Hu, Chip-Hong Chang:
A Practical Man-in-the-Middle Attack on Deep Learning Edge Device by Sparse Light Strip Injection into Camera Data Lane. 1-6 - Chaohui Xu, Wenye Liu, Yue Zheng, Si Wang, Chip-Hong Chang:
Inconspicuous Data Augmentation Based Backdoor Attack on Deep Neural Networks. 1-6 - Cory E. Merkel:
Enhancing Adversarial Attacks on Single-Layer NVM Crossbar-Based Neural Networks with Power Consumption Information. 1-6 - Aman Sinha
MSIM: A Highly Parallel Near-Memory Accelerator for MinHash Sketch. 1-6 - Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera:
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. 1-6 - Pragya Laad, Olivier Rizzo:
Divided by Designs, United by Flow-Uniquified, modular and automated approach to improve design efficiency. 1-2 - Markus Graber, Klaus Hofmann:
A Versatile & Adjustable 400 Node CMOS Oscillator Based Ising Machine to Investigate and Optimize the Internal Computing Principle. 1-6 - Lekshmi C, Anmol Khatri, Sourav Saha, Shivangi Gupta, Raj Yadav, Rakshit Bazaz:
I/O Constraints Optimization using Machine Learning. 1-6 - Weiming Hu, Yi Zhou, Ying Quan, Yuanfeng Wang, Xin Lou:
Cache-locality Based Adaptive Warp Scheduling for Neural Network Acceleration on GPGPUs. 1-6 - Guangxian Zhu, Huijia Wang, Yirong Kan, Zheng Chen, Ming Huang, Md. Altaf-Ul-Amin, Naoaki Ono, Shigehiko Kanaya, Renyuan Zhang, Yasuhiko Nakashima:
A Stochastic Coding Method of EEG Signals for Sleep Stage Classification. 1-6 - He Li, Adrian Wonfor, Amanda Weerasinghe, Muataz Alhussein, Yupeng Gong, Richard V. Penty:
Quantum Key Distribution Post-processing: A Heterogeneous Computing Perspective. 1-6 - Prasenjit Ray, V. Sai Prashant, Bindu P. Rao:
Machine Learning Based Parameter Tuning for Performance and Power optimization of Multisource Clock Tree Synthesis. 1-2 - Farehe Giahi, Sebastian Rachuj, Dietmar Fey:
Investigating SAMV Regarding its Suitability For FPGAs. 1-6 - Xiaotian Ma, Kevin Han, Yucheng Yang, Ronald F. DeMara, Yu Bai:
Hardware Oriented Strip-wise Optimization (HOSO) Framework for Efficient Deep Neural Network. 1-6 - Prangon Das, Purab Ranjan Sutradhar, Mark A. Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly:
Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware. 1-6 - Raphael Weber, Nico Adler, Thomas Wilhelm, Andreas Sailer, Clemens Reichmann:
Towards Automating a Software-Centered Development Process that considers Timing Properties. 1-6 - Javed S. Gaggatur:
A Duty Cycle Error Reduction with 1-point Calibration achieving 0.017UI in 7.2Gbps HBM3 DRAM Data Read. 1-6 - Claus Kestel, Christoph Frisch, Michael Pehl, Norbert Wehn:
Towards More Secure PUF Applications: A Low-Area Polar Decoder Implementation. 1-6 - Santlal Prajaprati, Manobendra Nath Mondal, Susmita Sur-Kolay:
Memristive Neural Network with Efficient In-Situ Supervised Training. 1-6 - Man Wu
GAND-Nets: Training Deep Spiking Neural Networks with Ternary Weights. 1-6 - Yunhao Ma
Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA. 1-5 - Yueyang Zheng, Chaolin Rao, Haochuan Wan
An RRAM-based Neural Radiance Field Processor. 1-5 - Javed S. Gaggatur:
Noise Analysis of CMOS Ring Oscillator-based Capacitance Measurement for Lab-on-Chip Application. 1-6 - Stefan Pechmann, Amelie Hagelauer:
A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays. 1-5 - Pragya Laad:
"High Five": Arm's first 5nm Silicon in flip-chip! 1-2 - Rahul Dutta, Ashish James, Salahuddin Raju, Yong-Joon Jeon, Chuan Sheng Foo, Kevin Tshun Chuan Chai:
Automated Deep Learning Platform for Accelerated Analog Circuit Design. 1-5 - Amir Khan, Jorge Fernández-Berni, Ricardo Carmona-Galán
An Architecture for On-Chip Face Recognition in a Compressive Image Sensor. 1-6 - Shenghou Ma, Paul Ampadu:
Efficient Low-bit-width Activation Function Implementations for Ultra Low Power SoCs. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-09-29 00:10 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: