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6th MTV 2005: Austin, TX, USA
- Magdy S. Abadir, Li-C. Wang:
Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA. IEEE Computer Society 2005, ISBN 0-7695-2627-6
Introduction
- Preface.
- Acknowledgement.
- Workshop Organizing Committee.
- Program Committee.
Architecture Description Languages
- Wei Qin, Sharad Malik
:
A Study of Architecture Description Languages from a Model-based Perspective. 3-11 - Brian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt
An Introduction to the Plasma Language. 12-22
SAT Applications
- Marc Herbstritt
On SAT-based Bounded Invariant Checking of Blackbox Designs. 23-28 - Tobias Schubert, Matthew D. T. Lewis, Bernd Becker
PaMira - A Parallel SAT Solver with Knowledge Sharing. 29-36
Debug and Diagnosis
- Paolo Bernardi
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets. 37-41 - Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
Post-Verification Debugging of Hierarchical Designs. 42-47 - Jennifer Dworak:
An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected Defects. 48-54 - Paolo Bernardi
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. 55-62
High Level Test and ATPG
- Bin Xue, D. M. H. Walker:
Is IDDQ Test of Microprocessors Feasible? 63-69 - Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli
A Pseudo-Deterministic Functional ATPG based on EFSM Traversing. 70-75 - Charles H.-P. Wen
Simulation Data Mining for Functional Test Pattern Justification. 76-83 - Jorge Campos, Hussain Al-Asaad:
Search-Space Optimizations for High-Level ATPG. 84-89 - John Mark Nolen, Rabi N. Mahapatra:
A TDM Test Scheduling Method for Network-on-Chip Systems. 90-98
Validation
- David Berner, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla:
Automated Extraction of Structural Information from SystemC-based IP for Validation. 99-104 - Soohong P. Kim:
Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors. 105-110 - Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova:
Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. 111-118 - Prabhat Mishra
Language-driven Validation of Pipelined Processors using Satisfiability Solvers. 119-126
Advances in Verification Methodology for Complex Designs
- Nicola Bombieri
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling. 127-132 - Daniel Große
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. 133-137 - Brian Kahne, Magdy S. Abadir:
Retiming Verification Using Sequential Equivalence Checking. 138-142
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