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ITC 2020: Washington, DC, USA
- IEEE International Test Conference, ITC 2020, Washington, DC, USA, November 1-6, 2020. IEEE 2020, ISBN 978-1-7281-9113-3
- Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, S. Y. Lee, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan (JV) Rajendran:
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits. 1-10 - Siyuan Chen, Jinwook Jung, Peilin Song, Krishnendu Chakrabarty
, Gi-Joon Nam:
BISTLock: Efficient IP Piracy Protection using BIST. 1-5 - Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton:
LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution. 1-10 - Chen He
Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In. 1-10 - Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton:
Knowledge Transfer for Diagnosis Outcome Preview with Limited Data. 1-9 - Hüseyin Sagirkaya, Gökhan Durgun:
Avionics Simulation Environment. 1-3 - Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Kojiro Ito, Masanori Hashimoto
Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing. 1-5 - Wei-Hao Chen, Chu-Chun Hsu, Shi-Yu Huang:
Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter. 1-8 - Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Lori Schramm, Cyrille Dray, El Mehdi Boujamaa, Khushal Gelda:
MBIST Supported Multi Step Trim for Reliable eMRAM Sensing. 1-5 - Fong-Jyun Tsai, Chong-Siao Ye
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. 1-10 - Mingye Li, Fangzhou Wang, Sandeep Gupta:
Data-driven fault model development for superconducting logic. 1-5 - Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang:
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. 1-9 - Andrew Stern, Dhwani Mehta, Shahin Tajik, Farimah Farahmandi, Mark M. Tehranipoor:
SPARTA: A Laser Probing Approach for Trojan Detection. 1-10 - Rajit Karmakar, Santanu Chattopadhyay
Hardware IP Protection Using Logic Encryption and Watermarking. 1-10 - Chen He
Stress, Test, and Simulation of Analog IOs on Automotive ICs. 1-10 - Hanbin Hu
Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns. 1-10 - Marampally Saikiran
Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage. 1-10 - Natalia Lylina, Ahmed Atteya, Chih-Hao Wang, Hans-Joachim Wunderlich:
Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks. 1-10 - Chen-Hung Wu, Cheng-Yun Hsieh
qATG: Automatic Test Generation for Quantum Circuits. 1-10 - Md Imran Momtaz, Chandramouli N. Amarnath, Abhijit Chatterjee:
Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks. 1-10 - Stephen Sunter, Michal Wolinski, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Nektar Xama, Jhon Gomez
Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs. 1-10 - Mohammad Nasim Imtiaz Khan, Swaroop Ghosh:
Assuring Security and Reliability of Emerging Non-Volatile Memories. 1-10 - Manu Baby, Bernd Büttner, Piet Engelke, Ulrike Pfannkuchen, Reinhard Meier, Jonathan Gaudet, Jean-François Côté, Givargis Danialy, Martin Keim, Lori Schramm:
IJTAG Through a Two-Pin Chip Interface. 1-5 - Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant:
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. 1-10 - Stefan Holst, Matthias Kampmann
Logic Fault Diagnosis of Hidden Delay Defects. 1-10 - Sang-Uck Ahn, Beom-Kyu Seo, Hyun-Woo Kim, Yeoun-Sook Shin, Hyung-Tae Kim, Ghil-Geun Oh, Young-Dae Kim:
Cost-Effective Test Method for screening out Unexpected Failure in High Speed Serial Interface IPs. 1-4 - Bharath Nandakumar, Sameer Chillarige, Anil Malik, Atul Chabbra, Nicholai L'Esperance, Robert Redburn:
Improved Chain Diagnosis Methodology for Clock and Control Signal Defect Identification. 1-9 - Leon Li-Yang Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng
TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning. 1-4 - Cesar A. Sánchez-Martínez, Paulo López-Meyer, Esdras Juárez-Hernández, Aaron Desiga-Orenday, Andrés Viveros-Wacher:
High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques. 1-5 - Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas:
On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors. 1-10 - Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee:
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. 1-10 - Trevor Kroeger, Wei Cheng
Cross-PUF Attacks on Arbiter-PUFs through their Power Side-Channel. 1-5 - Gabriele Boschi, Elisa Spano, Hayk T. Grigoryan, Arun Kumar, Gurgen Harutyunyan:
Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications. 1-6 - Fei Su, Prashant Goteti, Min Zhang:
Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics. 1-10 - Zeye Liu, R. D. Shawn Blanton:
High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips. 1-10 - Wei Gao, Tao Jing:
Modeling Accuracy of Wideband Power Amplifiers with Memory effects via Measurements. 1-7 - Safa Mhamdi, Patrick Girard
A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. 1-10 - Maxim Ladnushkin:
Flip-flops fanout splitting in scan designs. 1-5 - Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick:
Modeling Novel Non-JTAG IEEE 1687-Like Architectures. 1-10 - Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers:
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults. 1-10 - Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Machine Intelligence for Efficient Test Pattern Generation. 1-5 - Haiying Ma, Ligang Lu, Haitao Qian, Jing Han, Xin Wen, Fanjin Meng, Rahul Singhal, Martin Keim, Yu Huang, Wu Yang:
Fast Bring-Up of an AI SoC through IEEE 1687 Integrating Embedded TAPs and IEEE 1500 Interfaces. 1-5 - Rafael B. Schvittz, Paulo F. Butzen
Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients. 1-9 - Riccardo Cantoro
Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors. 1-5 - Yueling Jenny Zeng, Li-C. Wang, Chuanhe Jay Shan, Nik Sumikawa:
Learning A Wafer Feature With One Training Sample. 1-10 - Irith Pomeranz:
Selecting Close-to-Functional Path Delay Faults for Test Generation. 1-5 - Muslum Emir Avci, Sule Ozev:
Design Optimization for N-port RF Network Reflectometers under Noise and Gain Imperfections. 1-10 - Jun Chen, Masanori Hashimoto
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction. 1-8 - Lizhou Wu, Siddharth Rao
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs. 1-10 - Mengyun Liu, Krishnendu Chakrabarty
Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption. 1-10 - Riccardo Cantoro
New Perspectives on Core In-field Path Delay Test. 1-5 - Ricardo Aquino Guazzelli, Laurent Fesquet:
At-speed DfT Architecture for Bundled-data Design. 1-9 - Hanson Peng, Mao-Yuan Hsia, Man-Ting Pang, I.-Y. Chang, Jeff Fan, Huaxing Tang, Manish Sharma, Wu Yang:
Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency. 1-4 - Srikanth Venkataraman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang:
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization. 1-10 - Steven J. Frederiksen, John Aromando
Automated Assertion Generation from Natural Language Specifications. 1-5 - Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, Xijiang Lin:
Test Challenges of Intel IA Cores. 1-5 - Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak:
X-Tolerant Tunable Compactor for In-System Test. 1-10 - Hans Martin von Staudt, Mohamed Anas Benhebibi, Jeff Rearick, Michael Laisne:
Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices. 1-10 - Renjian Pan, Zhaobo Zhang, Xin Li, Krishnendu Chakrabarty
Unsupervised Root-Cause Analysis for Integrated Systems. 1-10 - Nidhi Agrawal, Min-Jian Yang, Constantinos Xanthopoulos, Vijayakumar Thangamariappan, Joe Xiao, Chee-Wah Ho, Keith Schaub, Ira Leventhal:
Automated Socket Anomaly Detection through Deep Learning. 1-5 - Suhasini Komarraju
Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning. 1-10 - Vijay Kiran Kalyanam, Eric Mahurin, Michael Spence, Jacob A. Abraham:
Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor. 1-10 - Arjun Chaudhuri, Jonti Talukdar
Functional Criticality Classification of Structural Faults in AI Accelerators. 1-5 - Hayoung Lee
Fail Memory Configuration Set for RA Estimation. 1-9 - Vadim Geurkov, Lev Kirischian:
A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing. 1-5 - M. Casarsa, Gurgen Harutyunyan, Yervant Zorian:
Test and Diagnosis Solution for Functional Safety. 1-5 - David Brauchler, Jennifer Dworak:
Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks. 1-10 - Mitchell A. Thornton:
Introduction to Quantum Computation Reliability. 1-10 - Sreeja Chowdhury, Rabin Yu Acharya, William Boullion, Andrew Felder, Mark Howard, Jia Di, Domenic Forte
A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates. 1-10 - Youngsu Oh, Dongmin Han, Byeongseon Go, Seungtaek Lee, Woosik Jeong:
Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test. 1-5 - Benoit Nadeau-Dostie, Luc Romain:
Memory repair logic sharing techniques and their impact on yield. 1-5 - Sarah Azimi
Digital Design Techniques for Dependable High Performance Computing. 1-10
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