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ISOCC 2011: Jeju, South Korea
- International SoC Design Conference, ISOCC 2011, Jeju, South Korea, November 17-18, 2011. IEEE 2011, ISBN 978-1-4577-0709-4
- Kaixue Ma, Shouxian Mou, Yang Lu, Kok Meng Lim, Kiat Seng Yeo:
A 60GHz defected ground power divider using SiGe BiCMOS technology. 1-4 - Keping Wang, Kaixue Ma, Kiat Seng Yeo:
Design consideration for 60 GHz SiGe power amplifier with ESD protection. 5-8 - Bharatha Kumar Thangarasu, Kaixue Ma, Kiat Seng Yeo, Shouxian Mou, Mahalingam Nagarajan:
A DC to 14GHz fully differential amplifier for wideband low power applications. 9-12 - Renjing Pan, Jiangmin Gu, Kiat Seng Yeo, Wei Meng Lim, Kaixue Ma:
SiGe BiCMOS power amplifiers for 60GHz ISM band applications. 13-16 - Fanyi Meng, Kiat Seng Yeo, Shanshan Xu, Kaixue Ma, Chee Chong Lim:
Wide center-tape balun for 60 GHz silicon RF ICs. 17-19 - Kenichi Okada:
A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver. 20-23 - Tetsuya Hirose:
Ultra-low power and low voltage circuit design for next-generation power-aware LSI applications. 24-27 - Atsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
A 21 V output charge pump circuit with appropriate well-bias supply technique in 0.18 μm Si CMOS. 28-31 - Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu:
A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS. 32-35 - Akira Tsuchiya, Takeshi Kuboki
, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera:
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. 36-39 - Yeong-Luh Ueng
A selective-input non-binary LDPC decoder architecture. 40-43 - Kai He, Jin Sha, Zhongfeng Wang:
Memory efficient decoder design of nonbinary LDPC codes. 44-47 - Yun Chen, Changsheng Zhou, Yuebin Huang, Shuangqu Huang, Xiaoyang Zeng:
Flexible and efficient FEC decoders supporting multiple transmission standards. 48-53 - Yuebin Huang, Chen Chen, Changsheng Zhou, Yun Chen, Xiaoyang Zeng:
A common flexible architecture for Turbo/LDPC codes. 54-57 - Chuan Zhang, Sang-Min Kim, Jin Sha:
Efficient Reed-Solomon based LDPC decoders. 58-61 - Dong-Hyun Hwang, Jung-Eun Song, Sang-Pil Nam, Hyo-Jin Kim, Tai-Ji An, Kwang-Soo Kim, Seung-Hoon Lee:
A range-scaled 13b 100MS/s 0.13μm CMOS SHA-free ADC based on a single reference. 62-65 - Daisuke Kanemoto, Toru Ido, Kenji Taniguchi:
A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing technique. 66-69 - Jinwoo Kim, Shin-Il Lim, Kwang Sub Yoon, Sangmin Lee:
Design of a 12-b asynchronous SAR CMOS ADC. 70-72 - Jin-Seon Kim, Tae-In Kwon, Gil-Cho Ahn, Yi-Gyeong Kim, Jong-Kee Kwon:
A ΔΣ ADC using 4-bit SAR type quantizer for audio applications. 73-75 - Arshad Hussain, Sai-Weng Sin
Hybrid loopfilter sigma-delta modulator with NTF zero compensation. 76-79 - Joohan Kim, Taewhan Kim:
A fine-grained timing driven synthesis of arithmetic circuits. 80-83 - Sik Kim, Kwang-Hyun Cho, Byeong Min:
An efficient GPIO block design methodology using formalized SFR description. 84-87 - Joonee Choung, Sangwoo Han, Byung-Su Kim, Juno Kim:
Variation-aware aging analysis with non-Gaussian parameters. 88-91 - Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Fast design space exploration for mixed hardware-software embedded systems. 92-95 - Inhyuk Choi, Taewoo Han, Ilwoong Kim, Sungho Kang:
Path search engine for fast optimal path search using efficient hardware architecture. 96-99 - Hi-Seok Kim, Sea-Ho Kim, Ki-Seok Chung:
FPGA implementation of unified kernel structure for MDCT/IMDCT in audio coding schemes. 100-103 - Da-Chiang Chang, Yuan-Chia Hsu, Ta-Yeh Lin, Ying-Zong Juang, Ibrahim Haroun:
Integrated Passive Device based RF circuit design for low-cost System-in-Package transceivers. 104-107 - Hung-Ju Wei, Chinchun Meng, Yi-Chen Lin:
Isolation performance of sub-harmonic Gilbert mixers. 108-111 - Shawn S. H. Hsu, Ming-Hsien Tsai:
Low-noise amplifiers with robust ESD protection for RF SOC. 112-115 - Tzu-Chao Yan, Chien-Nan Kuo:
Design of millimeter-wave CMOS frequency tripler. 116-119 - Chin-Fu Li, Chang-Ming Lai, Ping-Chuan Chiang, Po-Chiun Huang:
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension. 120-123 - Ding-Ming Kwai, Ka-Yi Yeh:
Developing through-silicon stacking process using 3-D CMOS imager as a test vehicle. 124-126 - Chiao-Ling Lung, Jui-Hung Chien, Yiyu Shi, Shih-Chieh Chang:
TSV fault-tolerant mechanisms with application to 3D clock networks. 127-130 - Jinn-Shyan Wang, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, Chingwei Yeh:
RSCE-aware ultra-low-voltage 40-nm CMOS circuits. 131-134 - Dae Hyun Kim, Rasit Onur Topaloglu
TSV density-driven global placement for 3D stacked ICs. 135-138 - Guojie Luo:
Physical hierarchy exploration of 3D processors. 139-141 - YongHwan Kim, Minseok Kang, Kyoung-Hwan Lim, Sangdo Park, Deokjin Joo, Taewhan Kim:
Clock design techniques considering circuit reliability. 142-145 - Masato Sakurai, Kiichi Niitsu
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. 146-149 - Teruki Nakasato, Toru Nakura, Kunihiro Asada:
Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. 150-153 - Christoph Kuznik, Wolfgang Müller:
Aspect enhanced functional coverage driven verification in the SystemC HDVL. 154-157 - Young-Nam Yun, Jae-Beom Kim, Nam-Do Kim, Byeong Min:
Beyond UVM for practical SoC verification. 158-162 - Tony Tae-Hyoung Kim, Zhi-Hui Kong:
Impacts of NBTI/PBTI on SRAM VMIN and design techniques for SRAM VMIN improvement. 163-166 - Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Low power semi-static TSPC D-FFs using split-output latch. 167-170 - Benjamin P. Wilkerson, Tae-Ho Kim, Jin-Ku Kang:
Low-power non-coherent data and power recovery circuit for implantable biomedical devices. 171-174 - Jungil Ahn, Jinwook Kim, Young Hwan Kim:
Leakage current modeling for GPGPU systems. 175-178 - Ali Valaee, Asim J. Al-Khalili:
SRAM read-assist scheme for high performanc low power applications. 179-182 - Shang-Hsien Yang, Chua-Chin Wang:
A 48-dB dynamic gain range/stage linear-in-dB low power Variable Gain Amplifier for direct-conversion receivers. 182-1 - Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada:
Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems. 183-186 - Kazuya Tanigawa, Tetsuo Hironaka:
Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area. 187-190 - Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Automated architecture exploration for low energy reconfigurable AGU. 191-194 - Yi Ge, Yoshimasa Takebe, Masahiko Toichi, Makoto Mouri, Makiko Ito, Yoshio Hirose, Hiromasa Takahashi:
A vector coprocessor architecture for embedded systems. 195-198 - Tomonori Izumi:
Research activities on reconfigurable systems in Japan. 199-202 - Yitao Ma, Tetsuo Endoh, Tadashi Shibata:
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching. 203-206 - Mochamad Asri, Naoki Fujieda, Kenji Kise:
Rethinking processor instruction fetch: Inefficiencies-cracking mechanism. 207-210 - Ki-woong Eom, Won-young Chung, Yong-Surk Lee:
A novel sequential tree algorithm based on the status of the processing nodes to reduce congestion. 211-214 - Jinook Song, In-Cheol Park
Division-less high-radix interleaved modular multiplication using a scaled modulus. 215-218 - Hsin-Chou Chi, Hsi-Che Tseng, Kun-Lin Tsai:
Design of timing-error-resilient systolic arrays for matrix multiplication. 219-222 - Shigekazu Miyawaki, Makoto Nakamura, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS. 223-226 - Nak Yoon Kim, Yong Moon:
A study on wide-band frequency synthesizer for advanced wireless communication. 227-230 - Jinsoo Rhim, Woo-Young Choi:
A 5-Gb/s low-power transmitter with voltage-mode output driver in 90nm CMOS technology. 231-234 - Sunwoo Yoon, JuYoung Jung, Dong-Hyun Baek:
A 34 dBm IP0.1dB SOI SP3T switch with an integrated negative-bias switch controller at 2.4 GHz. 235-237 - Jongsik Kim, Hyunchol Shin:
Design considerations for cognitive radio based CMOS TV white space transceivers. 238-241 - Jinna Yan, Kok Meng Lim, Jiangmin Gu, Keping Wang, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo:
A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process. 246-249 - Yuki Torigai, Minoru Watanabe:
Triple module redundancy scheme on an optically reconfigure gate array. 250-253 - Kok Meng Lim, Jiangmin Gu, Jinna Yan, Wei Meng Lim, Yang Lu, Kiat Seng Yeo:
Ultra low power active 60 GHz Bi-CMOS down-conversion mixer. 254-257 - Zhenghao Lu, Xiaopeng Yu
A 60GHz BiCMOS self-demodulator with injection locked oscillator. 258-261 - Sangkyun Park, Seonyoung Lee, Soojin Kim, Kyeongsoon Cho:
Design of AdaBoost classifier circuit using Haar-like features for automobile applications. 262-265 - Xuan Cheng, Huijie Zhao, Yonglong Dai, Xiaokang Liu:
Image acquisition design of the AOTF imaging spectrometer based on SOPC. 266-269 - Sung Dae Kim, Myung Hoon Sunwoo:
Efficient program control schemes for Motion Estimation specific processor. 270-273 - Sung In Cho, Hi-Seok Kim, Young Hwan Kim:
Two-step local dimming for image quality preservation in LCD displays. 274-277 - Seunghyun Cho, Seongmo Park, Nak-Woong Eum:
A 166.7 Mhz 1920×1080 60fps H.264/SVC video decoder. 278-281 - Yun Yang:
Effective readout pixel sensor circuit design for infrared focal plane array and three-dimension image MEMS VLSI system. 286-289 - Jae-Hwan Kim, Ji-Yong Um, Jae-Yoon Sim, Hong-June Park:
Time-interleaved sample clock generator for ultrasound beamformer application. 290-293 - Jinbo Wan, Hans G. Kerkhoff:
Boosted gain programmable Opamp with embedded gain monitor for dependable SoCs. 294-297 - Priyanka Kabara, Sanket Thakur, Gururaj Saileshwar, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
CMOS low-noise signal conditioning with a novel differential "resistance to frequency" converter for resistive sensor applications. 298-301 - Youngjoo Lee
Statistical modeling of capacitor mismatch effects for successive approximation register ADCs. 302-305 - Chun Zhao, W. Zhang, C. Z. Zhao, Ka Lok Man, Taikyeong T. Jeong, J. K. Seon, Y. Lee:
Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process. 306-309 - Eng Gee Lim
A novel radio propagation and radiation model of the wireless capsule endoscopy in human gastro-intestine (GI) tract. 310-312 - Chun Zhao, W. Pan, C. Z. Zhao, Ka Lok Man, J. Choi, J. Chang:
Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology. 313-316 - Mouna Karmani, Ka Lok Man, Chiraz Khedhiri, Belgacem Hamdi:
Design for testability in nano-CMOS analog integrated circuits using a new design analog checker. 317-320 - Ka Lok Man, Jieming Ma
Design, analysis, tools and applications for programmable high-speed and power-aware 4G processors. 321-324 - Neena A. Gilda, Sandeep Goud Surya, Sanjay Joshi, Viral Thaker, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao:
A low-cost, ultra sensitive hand-held system for explosive detection using piezo-resistive micro-cantilevers. 325-328 - Didier Pribat
A quick overview of carbon nanotubes and graphene applications for future electronics. 329-332 - Hong Zhu, Volkan Kursun
Symmetrical triple-threshold-voltage nine-transistor SRAM circuit with superior noise immunity and overall electrical quality. 333-336 - Jaeha Kung
Compact thermal models: Assessment and pitfalls. 337-340 - Masahiro Fukui, Yoriaki Nagata, Shuji Tsukiyama:
A power grid optimization algorithm considering timing degradation by NBTI. 341-344 - Jae-Won Park, Jin Ha Hwang, Won-young Chung, Seung-Woo Lee, Yong Surk Lee:
Design time stamp hardware unit supporting IEEE 1588 standard. 345-348 - Christian Brehm, Thomas Ilnseher, Norbert Wehn
A scalable multi-ASIP architecture for standard compliant trellis decoding. 349-352 - Jinho Lee
3D network-on-chip with wireless links through inductive coupling. 353-356 - Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata:
10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control. 357-360 - Yangsu Kim, Kyuseung Han, Kiyoung Choi:
A host-accelerator communication architecture design for efficient binary acceleration. 361-364 - Eun-Gu Jung, Daewan Han, Jeong-Gun Lee:
Low area and high speed SHA-1 implementation. 365-367 - Yihu Xu, Myoung-Seob Lim:
An efficient design of split-radix FFT pruning for OFDM based Cognitive Radio system. 368-372 - Jiemin Zhou, Mengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara:
A novel charge sharing charge pump for energy harvesting application. 373-376 - Orlando Lazaro, Gabriel Alfonso Rincón-Mora:
Minimizing MOSFET power losses in near-field electromagnetic energy-harnessing ICs. 377-380 - Sangdo Park, Taewhan Kim:
An energy-optimal algorithm for temperature-aware idle time distribution considering mode transition overhead. 381-384 - Suhwan Kim, Gabriel A. Rincón-Mora, Dongwon Kwon:
Extracting the frequency response of switching DC-DC converters in CCM and DCM from time-domain simulations. 385-388 - Xuan-Dien Do, Chang-Jin Jeong, Huy-Hieu Nguyen, Seok-Kyun Han, Sang-Gug Lee:
A high efficiency piezoelectric energy harvesting system. 389-392 - Ning Zhu, Wang Ling Goh, Kiat Seng Yeo:
Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant Applications. 393-396 - Omer Vikinski, Ram Ben-Ezra, Jimmy Huat Since Huang:
Enhancing circuits and systems supply noise sensitivity characterization using on-package droop inducers. 397-400 - Ho-Hsin Yeh, Ji-Chen Huang, Yu-Chen Kuo, Klaus Y. J. Hsu:
Design of low-power receiver front-end IC for low-frequency wireless time signal broadcast system. 401-404 - Jae-Won Nam, Young-Deuk Jeon, Seok-Ju Yun, Tae Moon Roh, Jong-Kee Kwon:
A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS. 405-407 - Yuan Cao, Xiangyu Zhang:
An on-chip hot pixel identification and correction approach in CMOS imagers. 408-411 - Qi Li, Tony T. Kim:
Analysis of SRAM hierarchical bitlines for optimal performance and variation tolerance. 412-415 - Myeong-Hoon Oh, Sung Nam Kim, Sungwoon Kim:
Design of asynchronous 2-phase ternary encoding protocol using multiple-valued logic. 416-419 - Hun Ho Ham, Jong-Hak Kim, Chan-Oh Park, Yong-Han Kim, Jun-Dong Cho
Noise reduction scheme of temporal and spatial filter for 3D video real-time processing. 420-423 - Youngdon Jung, Jisu Kim, Kyungho Ryu, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang:
MTJ based non-volatile flip-flop in deep submicron technology. 424-427 - Ji-Hoon Kim:
Design of TETRA Release 2 turbo decoder with low-complexity hardware interleaver. 428-431 - Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee, Jin-Gyun Chung:
Low-complexity filter and interpolator design for ATSC DTV systems. 432-435 - Jae-Jin Lee, Nak-Woong Eum:
Application specific processor for multi-standard video decoding. 436-439 - Ho Joon Lee, Kyung Ki Kim:
Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits. 440-443 - Joonhong Park, Hyuk Ryu, Donghyun Baek
77 GHz signal generator with CMOS technology for automotive radar application. 444-445 - Edward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim:
A design approach of a Parametric Measurement Unit on to a 600MHz DCL. 446-449 - Peiwen He, Wei Wang, Ken Choi, Jonghyun Lee, Soohyun Kim:
Prototyping circuit design for Dielectric Electroactive Polymers energy harvesting. 450-453 - Fanyi Meng, Kiat Seng Yeo, Shanshan Xu, Kaixue Ma, Chee Chong Lim:
Wide center-tape balun for 60 GHz silicon RF ICs. 454-456
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