default search action
IESS 2015: Foz do Iguaçu, Brazil
- Marcelo Götz
, Gunar Schirner, Marco Aurélio Wehrmeister
System Level Design from HW/SW to Memory for Embedded Systems - 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3-6, 2015, Proceedings. IFIP Advances in Information and Communication Technology 523, Springer 2017, ISBN 978-3-319-90022-3
Cyber-Physical Systems
- Maurício Fontana de Vargas
Ontological User Modeling for Ambient Assisted Living Service Personalization. 3-14 - Érico Nunes, Lucas P. Behnck, Carlos Eduardo Pereira
Multi-Agent Based Implementation of an Embedded Image Processing System in FPGA for Precision Agriculture Using UAVs. 15-26 - Alexander Jungmann, Jan Jatzkowski, Bernd Kleinjohann:
Combining Service-Oriented Computing with Embedded Systems - A Robotics Case Study. 27-37 - Luís Feliphe Silva Costa, Alisson V. Brito
Integration of Robot Operating System and Ptolemy for Design of Real-Time Multi-robots Environments. 38-47
System-Level Design
- Lydia Jaß, Paula Herber:
Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving. 51-63 - Marcus Mikulcak
Timed Path Conditions in MATLAB/Simulink. 64-76 - Gregor Nitsche
Structural Contracts - Motivating Contracts to Ensure Extra-Functional Semantics. 77-87 - Tayfun Gezgin, Björn Koopmann
Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique. 88-99
Multi/Many-Core System Design
- Jan Jatzkowski, Márcio Eduardo Kreutz, Achim Rettberg:
Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systems. 103-115 - Andrés Goens
Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs. 116-127 - Ran Hao, Nasibeh Teimouri, Kasra Moazzemi, Gunar Schirner:
Modeling and Analysis of SLDL-Captured NoC Abstractions. 128-141
Memory System Design
- Majid Sabbagh, Hamed Tabkhi, Gunar Schirner:
Taming the Memory Demand Complexity of Adaptive Vision Algorithms. 145-158 - Paulo C. Santos
HMC and DDR Performance Trade-offs. 159-171 - Gustavo Girão, Flávio Rech Wagner:
Managing Cache Memory Resources in Adaptive Many-Core Systems. 172-182
Embedded HW/SW Design and Applications
- Malte Falk, Stefan Walter, Achim Rettberg:
A UML Profile to Couple the Production Code Generator TargetLink with UML Design Tools. 185-196 - Kasra Moazzemi, Smit Patel, Shen Feng, Gunar Schirner:
Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables. 197-209 - Vitor V. Bandeira
Low Latency FPGA Implementation of Izhikevich-Neuron Model. 210-217 - Éricles Sousa
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. 218-229
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: