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HLDVT 2007: Irvine, CA, USA
- IEEE International High Level Design Validation and Test Workshop, HLDVT 2007, Irvine, CA, USA, November 7-9, 2007. IEEE Computer Society 2007, ISBN 978-1-4244-1480-2
Multiprocessors I
- Mohammad Hosseinabady
, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan:
Reliable network-on-chip based on generalized de Bruijn graph. 3-10 - Kiran Ramineni, Ian G. Harris, Shireesh Verma:
Improving feasible interactions among multiple processes. 11-18
Multiprocessors II
- Eric Cheung, Harry Hsieh, Felice Balarin:
Framework for fast and accurate performance simulation of multiprocessor systems. 21-28 - Lucky L. Chi Yu Lo, Samar Abdi:
Automatic TLM generation for C-Based MPSoC design. 29-36 - Eric Cheung, Harry Hsieh, Felice Balarin:
Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip. 37-44
Invited Session: Post-Silicon Validation
- Jai Kumar, Catherine Ahlschlager, Peter Isberg:
Post-silicon verification methodology on Sun's UItraSPARC T2. 47 - Shakti Kapoor:
Challenges in post-silicon verification of IBM's Cell/B.E. and other game processors. 48-52 - Tommy Bojan, Igor Frumkin, Robert Mauri:
Intel's Post Silicon functional validation approach. 53-56
Debug
- Tao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li:
Bug analysis and corresponding error models in real designs. 59-64 - Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov:
Automatic error diagnosis and correction for RTL designs. 65-72 - Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh:
Bridging RTL and gate: correlating different levels of abstraction for design debugging. 73-80
Test Generation
- Deepak Mathaikutty, Sumit Ahuja, Ajit Dingankar, Sandeep K. Shukla
Model-driven test generation for system level validation. 83-90 - Mingsong Chen, Prabhat Mishra
Towards RTL test generation from SystemC TLM specifications. 91-96 - Bijan Alizadeh, Masahiro Fujita:
A novel formal approach to generate high-level test vectors without ILP and SAT solvers. 97-104
Formal Verification
- Xiaofang Chen, Yu Yang, Michael Delisi, Ganesh Gopalakrishnan, Ching-Tsun Chou:
Hierarchical cache coherence protocol verification one level at a time through assume guarantee. 107-114 - Joseph Buck, Dong Wang, Yunshan Zhu:
Formal model construction using HDL simulation semantics. 115-122 - Noureddine Chabini, Wayne H. Wolf:
An approach for computing the initial state for retimed synchronous sequential circuits. 123-130
Invited Session: High Level Design
- Gérard Berry:
Circuit design and verication with Esterel v7 and Esterel Studio. 133-136 - Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel:
FFT Compiler: from math to efficient hardware HLDVT invited short paper. 137-139 - Krste Asanovic:
Transactors for parallel hardware and software co-design. 140-142
Coverage Directed Validation
- Tommy Bojan, Manuel Aguilar Arreola, Eran Shlomo, Tal Shachar:
Functional coverage measurements and results in post-Silicon validation of Core™2 duo family. 145-150 - Onur Guzey, Li-C. Wang
Coverage-directed test generation through automatic constraint extraction. 151-158 - Shireesh Verma, Ian G. Harris, Kiran Ramineni:
Automatic generation of functional coverage models from CTL. 159-164
Panel
- Sunil Kakkar, Janick Bergeron, Brian Bailey, Harry Foster, Ian Harris:
Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test. 167-168
Embedded Systems
- Alfredo Benso
Automating the IEEE std.1500 compliance verification for embedded cores. 171-178 - Marco Murciano, Massimo Violante:
Validating the dependability of embedded systems through fault injection by means of loadable kernel modules. 179-186 - Franco Fummi, Giovanni Perbellini, Davide Quaglia
AME: an abstract middleware environment for validating networked embedded systems applications. 187-194
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