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DFT 2013: New York City, NY, USA
- 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013. IEEE Computer Society 2013
- Irith Pomeranz:
Classes of difficult-to-diagnose transition fault clusters. 1-6 - Kun Bian, D. M. H. Walker, Sunil P. Khatri, Shayak Lahiri:
Mixed structural-functional path delay test generation and compaction. 7-12 - Cristiana Bolchini
, Elisa Quintarelli
A data mining approach to incremental adaptive functional diagnosis. 13-18 - Naseef Mansoor, Amlan Ganguly, Manoj Prashanth Yuvaraj:
An energy-efficient and robust millimeter-wave Wireless Network-on-Chip architecture. 19-24 - Lanfang Tan, Ying Tan, Jianjun Xu:
CFEDR: Control-flow error detection and recovery using encoded signatures monitoring. 25-32 - Rance Rodrigues, Sandip Kundu:
A low power architecture for online detection of execution errors in SMT processors. 33-38 - Atefe Dalirsani, Michael A. Kochte, Hans-Joachim Wunderlich:
SAT-based code synthesis for fault-secure circuits. 39-44 - Michael A. Skitsas, Chrysostomos Nicopoulos
DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems. 45-51 - Kazuteru Namba, Fabrizio Lombardi:
A novel scheme for concurrent error detection of OLS parallel decoders. 52-57 - Cristiana Bolchini
Run-time mapping for reliable many-cores based on energy/performance trade-offs. 58-64 - Muhammad Aamir Khan, Hans G. Kerkhoff:
Analysing degradation effects in charge-redistribution SAR ADCs. 65-70 - Jianghao Guo, Qiang Han, Wen-Ben Jone, Yu-Liang Wu:
A cross-layer fault-tolerant design method for high manufacturing yield and system reliability. 71-76 - Patryk Skoncej:
Fault Injection Framework for embedded memories. 77-82 - Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani, Giovanni De Micheli:
A fast TCAD-based methodology for Variation analysis of emerging nano-devices. 83-88 - Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
Low power and high speed current-mode memristor-based TLGs. 89-94 - Alexandru Paler, Josef Kinseher, Ilia Polian, John P. Hayes:
Approximate simulation of circuits with probabilistic behavior. 95-100 - Chen Liu, Jeyavijayan Rajendran, Chengmo Yang, Ramesh Karri
Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling. 101-106 - Stefano Campitelli, Marco Ottavi
F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments. 107-111 - Arwa Ben Dhia, Lirida A. B. Naviner
Evaluating CLB designs under multiple SETs in SRAM-based FPGAs. 112-117 - Veit Kleeberger
Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling. 118-124 - Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba:
Efficient compression of x-masking control data via dynamic channel allocation. 125-130 - Emanuel Dogaru, Filipe Vinci dos Santos, William Rebernak:
LMS-based RF BIST architecture for multistandard transmitters. 131-136 - Rafal Baranowski, Alejandro Cook, Michael E. Imhof, Chang Liu, Hans-Joachim Wunderlich:
Synthesis of workload monitors for on-line stress prediction. 137-142 - Elena I. Vatajelu
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. 143-148 - Alexandre Sarafianos, Mathieu Lisart, Olivier Gagliano, Valerie Serradeil, Cyril Roscian, Jean-Max Dutertre
Robustness improvement of an SRAM cell against laser-induced fault injection. 149-154 - Ting An, Lirida Alves de Barros Naviner
A low cost reliable architecture for S-Boxes in AES processors. 155-160 - Meilin Zhang, Paul Ampadu:
Variation-tolerant cache by two-layer error control codes. 161-166 - Pedro Reviriego, Shih-Fu Liu
Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes. 167-171 - Glenn H. Chapman, Rohit Thomas, Israel Koren, Zahava Koren:
Improved image accuracy in Hot Pixel degraded digital cameras. 172-177 - Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
Impact of mid-bond testing in 3D stacked ICs. 178-183 - Yu-Wei Lee, Nur A. Touba:
Unified 3D test architecture for variable test data bandwidth across pre-bond, partial stack, and post-bond test. 184-189 - Hassan Salmani, Mohammad Tehranipoor:
Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral level. 190-195 - Gustavo K. Contreras, Md. Tauhidur Rahman
Secure Split-Test for preventing IC piracy by untrusted foundry and assembly. 196-203 - Amir-Pasha Mirbaha, Jean-Max Dutertre
Differential analysis of Round-Reduced AES faulty ciphertexts. 204-211 - Matheus T. Moreira, Bruno S. Oliveira, Fernando Gehm Moraes
Charge sharing aware NCL gates design. 212-217 - Kaikai Liu, Hao Cai, Ting An, Lirida A. B. Naviner
Reliability analysis of combinational circuits with the influences of noise and single-event transients. 218-223 - Caleb Serafy, Ankur Srivastava
Online TSV health monitoring and built-in self-repair to overcome aging. 224-229 - Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi:
Impact of PVT variation on delay test of resistive open and resistive bridge defects. 230-235 - Jianli Li, Qingping Tan:
SmartInjector: Exploiting intelligent fault injection for SDC rate analysis. 236-242 - Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas
Built-in Self-Repair in a 3D die stack using programmable logic. 243-248 - Soroush Khaleghi, Wenjing Rao:
Spare sharing network enhancement for scalable systems. 249-254 - Aleksandar Simevski, Rolf Kraemer, Milos Krstic
Automated integration of fault injection into the ASIC design flow. 255-260 - J.-Y. Hung, Noh-Jin Park, K. M. George, Nohpill Park:
Modeling and analysis of repair and maintenance processes in Fault Tolerant Systems. 261-265 - Qiaoyan Yu, Jonathan Frey:
Exploiting error control approaches for Hardware Trojans on Network-on-Chip links. 266-271 - Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel:
Framework for dynamic estimation of power-supply noise and path delay. 272-277 - Masayoshi Yoshimura, Amy Ogita, Toshinori Hosokawa:
A smart Trojan circuit and smart attack method in AES encryption circuits. 278-283 - Natesh Ganesh, Neal G. Anderson:
On-chip error correction with unreliable decoders: Fundamental physical limits. 284-289 - Manoj Kumar
Reconfigurable distributed fault tolerant routing algorithm for on-chip networks. 290-295 - Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
BIST for logic and local interconnect resources in a novel mesh of cluster FPGA. 296-301 - Kouta Maebashi, Kazuteru Namba, Masato Kitakami:
Testing of switch blocks in TSV-reduced Three-Dimensional FPGA. 302-307
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