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26th DDECS 2023: Tallinn, Estonia
- Maksim Jenihhin, Hana Kubátová, Nele Metens, Jaan Raik, Foisal Ahmed, Jan Belohoubek:
26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023. IEEE 2023, ISBN 979-8-3503-3277-3 - Adebayo Omotosho
, Sirine IIahi, Ernesto Cristopher Villegas Castillo
Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype. 1-6 - Michal Kekely, Jan Korenek:
Optimizing Packet Classification on FPGA. 7-12 - Ognjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic:
Active Wire Fences for Multitenant FPGAs. 13-20 - Paolo Bernardi, Gabriele Filipponi
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults. 21-26 - Swantje Plambeck
Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models. 27-32 - Robert Hülle, Petr Fiser, Jan Schmidt:
Reducing Output Response Aliasing Using Boolean Optimization Techniques. 33-38 - Luigi Capogrosso
Split-Et-Impera: A Framework for the Design of Distributed Deep Learning Applications. 39-44 - Michal Pinos, Vojtech Mrazek, Lukás Sekanina:
Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. 45-50 - Ali Monavari Bidgoli, Sepideh Fattahi, Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Masoud Daneshtalab:
NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures. 51-56 - Jonas Bertels
Hardware Acceleration of FHEW. 57-60 - Fabio A. Velarde Gonzalez, Lukas Hahne, Katrin Ortstein, André Lange, Sonja Crocoll:
Supporting analog design for reliability by efficient provision of reliability information to designers. 61-64 - Christian Fibich, Martin Horauer, Roman Obermaisser:
Characterization of Interconnect Fault Effects in SRAM-based FPGAs. 65-68 - Khakim Akhunov
LUTIC: A CRAM-based Architecture for Power Failure Resilient In-Memory Computing. 69-72 - Rune Krauss
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes. 73-78 - Elias Trommer, Bernd Waschneck, Akash Kumar:
High-Throughput Approximate Multiplication Models in PyTorch. 79-82 - Nooshin Nosrati, Zainalabedin Navabi:
A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators. 83-86 - Luigi Capogrosso
HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package. 87-90 - Vojtech Mrazek
Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial). 91-92 - Carl Riehm, Christoph Frisch, Florin Burcea, Matthias Hiller, Michael Pehl, Ralf Brederlow
Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations. 93-98 - Maryam Saadat-Safa, Tahoura Mosavirik, Shahin Tajik
Counterfeit Chip Detection using Scattering Parameter Analysis. 99-104 - Marcel Merten, Muhammad Hassan, Rolf Drechsler:
Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques. 105-110 - Daniel Öhlinger
A Digital Delay Model Supporting Large Adversarial Delay Variations. 111-117 - Mohamed El Bouazzati, Russell Tessier, Philippe A. Tanguy, Guy Gogniat:
A Lightweight Intrusion Detection System against IoT Memory Corruption Attacks. 118-123 - Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik:
APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. 124-127 - Jure Vreca, Anton Biasizzo:
A Configurable Mixed-Precision Convolution Processing Unit Generator in Chisel. 128-131 - Sergio Vinagrero Gutierrez, Pietro Inglese, Giorgio Di Natale, Elena-Ioana Vatajelu:
Open Automation Framework for Complex Parametric Electrical Simulations. 132-135 - Zahra Hojati, Zainalabedin Navabi:
A Low-Cost Combinational Approximate Multiplier. 136-139 - Nicolas Gerlin, Endri Kaja, Fabian Vargas, Li Lu, Anselm Breitenreiter
Bits, Flips and RISCs. 140-149 - Dominic Korner, Andreas Kramer, Klaus Hofmann, Felix Hausch:
Standalone Area Optimized ASIC Tag Powered and Programmable by Light for Identification of Novel Drug Candidates. 150-154 - Martin Hurta
MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. 155-160 - Joseline Heuer, Rene Krenz-Baath, Roman Obermaisser:
Verifying Bio-Electronic Systems. 161-166 - Letícia Maria Veiras Bolzani:
Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing? 167-168 - Robert Limas Sierra, Juan-David Guerrero-Balaguera
A Reliability-aware Environment for Design Exploration for GPU Devices. 169-174 - Eleonora Vacca, Sarah Azimi, Luca Sterpone:
A Comprehensive Analysis of Transient Errors on Systolic Arrays. 175-180 - Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio:
Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator. 181-186
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last updated on 2024-11-26 20:32 CET by the dblp team
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