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20th DDECS 2017: Dresden, Germany
- Manfred Dietrich, Ondrej Novák:
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2017, Dresden, Germany, April 19-21, 2017. IEEE 2017, ISBN 978-1-5386-0472-4 - Martin Hunek, Zdenek Plíva:
Design and optimisation of NiTi pressure gauge. 1-3 - Saurabh Chaturvedi, Mladen Bozanic, Saurabh Sinha:
A 50 GHz SiGe BiCMOS active bandpass filter. 2-5 - Andreas Rauchenecker, Robert Wille:
An efficient physical design of fully-testable BDD-based circuits. 6-11 - Tohid Taghizad Gogjeh Yaran, Suleyman Tosun:
Improving combinational circuit resilience against soft errors via selective resource allocation. 12-15 - Tino Flenker, Görschwin Fey
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Mapping abstract and concrete hardware models for design understanding. 16-21 - Mustafa Ozgul, Florian Deeg, Sebastian M. Sattler:
Mealy-to-moore transformation. 22-27 - Imran Wali, Marcello Traiola
Towards approximation during test of Integrated Circuits. 28-33 - Matthias Kampmann
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. 35-41 - Davide Dicorato, Petr Pfeifer, Heinrich Theodor Vierhaus:
Fault detection and self repair in Hsiao-code FEC circuits. 42-47 - Siavoosh Payandeh Azad, Behrad Niazmand
From online fault detection to fault management in Network-on-Chips: A ground-up approach. 48-53 - Ondrej Novák, Zdenek Plíva
Logic testing with test-per-clock pattern loading and improved diagnostic abilities. 54-59 - Marko S. Andjelkovic
An analysis of the operation and SET robustness of a CMOS pulse stretching circuit. 61-66 - Pawel Narczyk, Krzysztof Siwiec
Analog front-end for precise human body temperature measurement. 67-72 - Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich:
Body biasing for analog design: Practical experiences in 22 nm FD-SOI. 73-78 - Michal Wolodzko, Wieslaw Kuzmicz
A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technology. 79-82 - Arash Barzinmehr
Energy-aware application-specific topology generation for 3D Network-on-Chips. 84-87 - Ondrej Kachman, Marcel Baláz:
Firmware Update Manager: A remote firmware reprogramming tool for low-power devices. 88-91 - Madis Kerner, Kalle Tammemäe:
Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator. 92-95 - Andreas Furtig, Georg Glaeser, Christoph Grimm
Novel metrics for Analog Mixed-Signal coverage. 97-102 - Michael Schwarz, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz:
Cycle-accurate software modeling for RTL verification of embedded systems. 103-108 - Feim Ridvan Rasim, Canan Kocar, Sebastian M. Sattler:
Structure-preserving modeling of safety-critical combinational circuits. 109-114 - Thomas Polzer, Florian Huemer
Measuring metastability using a time-to-digital converter. 116-121 - Oliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic
Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins. 122-126 - Michal Sovcik
Ultra-low-voltage driver for large load capacitance in 130nm CMOS technology. 127-132 - Ivo Hálecek, Petr Fiser, Jan Schmidt:
Are XORs in logic synthesis really necessary? 134-139 - Miroslav Siro, Dominik Macko
PMS2UPF: An automated transition from ESL to RTL power-intent specification. 140-144 - Marcello Traiola
Formal Design Space Exploration for memristor-based crossbar architecture. 145-150 - Raimund Ubar
A scalable technique to identify true critical paths in sequential circuits. 152-157 - Lei Xie, Hoang Anh Du Nguyen, Jintao Yu
On the robustness of memristor based logic gates. 158-163 - Norbert Druml, Christoph Ehrenhöfer, Walter Bell, Christian Gailer, Hannes Plank, Thomas Herndl, Gerald Holweg:
A fast and flexible HW/SW co-processing framework for Time-of-Flight 3D imaging. 165-170 - Radek Isa, Jirí Matousek:
A novel architecture for LZSS compression of configuration bitstreams within FPGA. 171-176 - Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki:
HLS design of a hardware accelerator for Homomorphic Encryption. 178-183 - Petr Socha
Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. 184-189 - Saya Ohira, Tetsuya Matsumura:
Design for three-dimensional sound processor using high-level synthesis. 190-193 - Patrick Russell, Jens Döge
Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC. 195-200 - Felix Mühlbauer
On hardware-based fault-handling in dynamically scheduled processors. 201-206 - Lukás Kohútka
Rocket Queue: New data sorting architecture for real-time systems. 207-212
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