• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 15 matches

• 2004
• 
  Helena Krupnova:
  Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience. DATE 2004: 1236-1243
• 
  Anne Bigot, Fabrice Charpentier, Helena Krupnova, Isabelle Sans:
  Deploying Hardware Platforms for SoC Validation: An Industrial Case Study. FPL 2004: 64-73
• 2002
• 
  Helena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid Morsi:
  How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project. FPL 2002: 26-35
• 2000
• 
  Helena Krupnova, Gabriele Saucier:
  FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. FPL 2000: 68-77
• 
  Helena Krupnova, Gabriele Saucier:
  FPGA Technology Snapshot: Current Devices and Design Tools. IEEE International Workshop on Rapid System Prototyping 2000: 200-
• 1999
• 
  Helena Krupnova, Gabriele Saucier:
  Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. DATE 1999: 587-
• 
  Helena Krupnova, Gabriele Saucier:
  Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. FPGA 1999: 251
• 
  Helena Krupnova, Gabriele Saucier:
  Hierarchical Interactive Approach to Partition Large Designs into FPGAs. FPL 1999: 101-110
• 
  Helena Krupnova, Christian Rabedaoro, Gabriele Saucier:
  FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. IEEE International Workshop on Rapid System Prototyping 1999: 128-133
• 1998
• 
  Helena Krupnova, B. Behnam, Gabriele Saucier:
  Block and IP Wrapping for Efficient Design on FPGAs (Abstract). FPGA 1998: 256
• 
  S. A. Senouci, Aadil Amoura, Helena Krupnova, Gabriele Saucier:
  Timing Driven Floorplanning on Programmable Hierarchical Targets. FPGA 1998: 85-92
• 
  Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier:
  A Knowledge-Based System for Prototyping on FPFAs. FPL 1998: 89-98
• 
  Helena Krupnova, Dinh Duc Anh Vu, Gabriele Saucier, Michel Boubal:
  Real Time Prototyping Method and a Case Study. International Workshop on Rapid System Prototyping 1998: 13-18
• 1997
• 
  Helena Krupnova, Ali Abbara, Gabriele Saucier:
  A Hierarchy-Driven FPGA Partitioning Method. DAC 1997: 522-525
• 
  Helena Krupnova, Christian Rabedaoro, Gabriele Saucier:
  Synthesis and Floorplanning for Large Hierarchical FPGAs. FPGA 1997: 105-111