• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 83 matches

• 2003
• 
  Soroush Abbaspour, Massoud Pedram, Payam Heydari:
  Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers. ISQED 2003: 261-266
• 
  Afshin Abdollahi, Farzan Fallah, Massoud Pedram:
  Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains. ISQED 2003: 49-54
• 
  Mohsen Alavi:
  Overview of Reliability Issues in Deep Sub-Micron Digital CMOS Technology and Their Interaction with Circuit Design Considerations. ISQED 2003: 12
• 
  Bijan Alizadeh, Mohammad Reza Kakoee:
  Using Integer Equations for High Level Formal Verification Property Checking. ISQED 2003: 69-74
• 
  Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas:
  Noise-Aware Driver Modeling for Nanometer Technology. ISQED 2003: 177-182
• 
  Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
  Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176
• 
  Wendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim, Madhavan Swaminathan:
  Modeling and Analysis of Power Distribution Networks for Gigabit Applications. ISQED 2003: 235-240
• 
  Terry Blanchard:
  Assessment of the OpenAccess Standard: Insights on the new EDA Industry Standard from Hewlett-Packard, a Beta Partner and Contributing Developer. ISQED 2003: 203-207
• 
  Duane S. Boning:
  Test Structures for Circuit Yield Assessment and Modeling. ISQED 2003: 8
• 
  Gustavo Marrero Callicó, Antonio Núñez, Rafael Peset Llopis, Ramanathan Sethuraman:
  Low-Cost and Real-Time Super-Resolution over a Video Encoder IP. ISQED 2003: 79-84
• 
  Marco Casale-Rossi:
  Enhancing the Silicon-Package Interface Through Their Concurrent Design and Verification. ISQED 2003: 10
• 
  Chien-In Henry Chen, Kiran George:
  Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. ISQED 2003: 111-116
• 
  Tom Chen, Amjad Hajjar:
  Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. ISQED 2003: 183-188
• 
  Geun Rae Cho, Tom Chen:
  Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ISQED 2003: 55-60
• 
  Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim:
  Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED 2003: 153-158
• 
  D. R. Cottrell, T. J. Grebinski:
  Interoperability Beyond Design: Sharing Knowledge between Design and Manufacturing. ISQED 2003: 214-219
• 
  Giuseppe Crisenza:
  Yield in flash memory: Methodology, modeling and design issues. ISQED 2003: 9
• 
  Gilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Sridhar Subramaniam, Hem Hingarh:
  The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data Exchange. ISQED 2003: 144-149
• 
  Petros Drineas, Yiorgos Makris:
  Concurrent Fault Detection in Random Combinational Logic. ISQED 2003: 425-430
• 
  F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh:
  Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. ISQED 2003: 119-124
• 
  Rich Evans:
  A Package Design Perspective, "It will be BGA and Flip-Chip". ISQED 2003: 11
• 
  Gary Feierbach, Vijay Gupta:
  True Coverage: A Goal of Verification. ISQED 2003: 75-78
• 
  Anna Fontanelli:
  An EDA Perspective, "We Need it Yesterday! ISQED 2003: 11
• 
  Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, David Pinto:
  New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains. ISQED 2003: 131-137
• 
  Rafik S. Guindi, Farid N. Najm:
  Design Techniques for Gate-Leakage Reduction in CMOS Circuits. ISQED 2003: 61-65
• 
  Puneet Gupta, Andrew B. Kahng:
  Quantifying Error in Dynamic Power Estimation of CMOS Circuits. ISQED 2003: 273-278
• 
  Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
  A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. ISQED 2003: 339-343
• 
  Jean-Pierre Heliot, Florent Parmentier, Marie-Pierre Baron:
  LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume Reduction. ISQED 2003: 85-89
• 
  Payam Heydari:
  Design and Analysis of Low-Voltage Current-Mode Logic Buffers. ISQED 2003: 293-298
• 
  Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
  Minimizing Inter-Clock Coupling Jitter. ISQED 2003: 333-338

skipping 53 more matches