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"High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications."

Junichi Sakamoto et al. (2024)

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DOI: 10.1109/TVLSI.2024.3402164

access: closed

type: Journal Article

metadata version: 2024-08-22

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  - https://dblp.org/rec/journals/tvlsi/SakamotoFAYM24
Junichi Sakamoto, Daisuke Fujimoto, Riku Anzai, Naoki Yoshida, Tsutomu Matsumoto:
High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1498-1511 (2024)

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