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"Zero-aware asymmetric SRAM cell for reducing cache power in writing zero."

Yen-Jen Chang, Feipei Lai, Chia-Lin Yang (2004)

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DOI: 10.1109/TVLSI.2004.831471

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - journals/tvlsi/ChangLY04
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  - https://dblp.org/rec/journals/tvlsi/ChangLY04
Yen-Jen Chang, Feipei Lai, Chia-Lin Yang:
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 827-836 (2004)

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