0.7Ge_0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology.">0.7Ge_0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology., dblp, computer science, bibliography, knowledge graph, author, editor, publication, conference, journal, book, thesis, database, collection, open data, bibtex">

default search action

combined dblp search
author search
venue search
publication search

ask others

"Design of Low Power Si0.7Ge0.3 Pocket Junction-Less ..."

Suman Lata Tripathi, Govind Singh Patel (2020)

> Home

Details and statistics

DOI: 10.1007/S11277-019-06978-8

access: closed

type: Journal Article

metadata version: 2021-07-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/wpc/TripathiP20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/wpc/TripathiP20
Suman Lata Tripathi, Govind Singh Patel:
Design of Low Power Si_0.7Ge_0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology. Wirel. Pers. Commun. 111(4): 2167-2176 (2020)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.