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"7.5 Gb/s monolithically integrated clock recovery circuit using PLL and ..."

Zhi-Gong Wang et al. (1994)

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DOI: 10.1109/4.297711

access: closed

type: Journal Article

metadata version: 2023-05-09

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  - https://dblp.org/rec/journals/jssc/WangBNHHKRS94
Zhi-Gong Wang, Manfred Berroth, Ulrich Nowotny, Peter Hofmann, Axel Hiilsmann, Klaus Köhler, Brian Raynor, Joachim Schneider:
7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-μm gate length quantum well HEMT's. IEEE J. Solid State Circuits 29(8): 995-997 (1994)

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