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"An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using ..."

Tae-Jin Kim et al. (2022)

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DOI: 10.1109/JSSC.2021.3140053

access: closed

type: Journal Article

metadata version: 2022-03-15

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  - https://dblp.org/rec/journals/jssc/KimPLLC22
Tae-Jin Kim, Jae-Woo Park, Hyun-Wook Lim, Jae-Youl Lee, Jung-Hoon Chun:
An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires. IEEE J. Solid State Circuits 57(3): 932-941 (2022)

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