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"0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port ..."

Hiroyuki Hara et al. (1992)

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DOI: 10.1109/4.165339

access: closed

type: Journal Article

metadata version: 2025-02-03

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  - journals/jssc/HaraSNSMNMMWSC92
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  - https://dblp.org/rec/journals/jssc/HaraSNSMNMMWSC92
Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba:
0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file. IEEE J. Solid State Circuits 27(11): 1579-1584 (1992)

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