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"Low Power 16 x 16 Bit Multiplier Design Using PAL-2N Logic Family."

H. H. Wong, K. T. Lau (2002)

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DOI: 10.1142/S021812660200032X

access: closed

type: Journal Article

metadata version: 2020-08-25

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  - https://dblp.org/rec/journals/jcsc/WongL02
H. H. Wong, K. T. Lau:
Low Power 16 x 16 Bit Multiplier Design Using PAL-2N Logic Family. J. Circuits Syst. Comput. 11(2): 155-164 (2002)

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