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"Improving power-awareness of pipelined array multipliers using ..."

Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara (2006)

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DOI: 10.1016/J.VLSI.2004.08.002

access: closed

type: Journal Article

metadata version: 2020-10-08

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Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara:
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design. Integr. 39(2): 90-112 (2006)

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