default search action

combined dblp search
author search
venue search
publication search

ask others

"A formal design methodology for synthesizing a clock signal with an ..."

Lulu Ge et al. (2015)

> Home

Details and statistics

DOI: 10.1109/SIPS.2015.7344975

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/sips/GeZZY15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/sips/GeZZY15
Lulu Ge, Chuan Zhang, Zhiwei Zhong, Xiaohu You:
A formal design methodology for synthesizing a clock signal with an arbitrary duty cycle of M/N. SiPS 2015: 1-6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.