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"15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array ..."

Daeyeon Kim et al. (2024)

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DOI: 10.1109/ISSCC49657.2024.10454501

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-19

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  dblp key:
  - conf/isscc/KimKSPPBDRBOWGK24
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  - https://dblp.org/rec/conf/isscc/KimKSPPBDRBOWGK24
Daeyeon Kim, Yusung Kim, Ayush Shrivastava, Gyusung Park, Anandkumar Mahadevan Pillai, Kunal Bannore, Tri Doan, Muktadir Rahman, Gwanghyeon Baek, Clifford Ong, Xiaofei Wang, Zheng Guo, Eric Karl:
15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia. ISSCC 2024: 278-280

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